OPTIMIZED PIXEL DESIGN FOR MITIGATING MIM IMAGE LAG

    公开(公告)号:US20240348946A1

    公开(公告)日:2024-10-17

    申请号:US18298975

    申请日:2023-04-11

    CPC classification number: H04N25/771 H04N25/59

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a pixel voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network includes a first LOFIC coupled between the floating diffusion and the first bias voltage source, and a second LOFIC coupled between the floating diffusion and the second bias voltage source. The first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased at an end of an integration period, and image charge discharged from the first LOFIC and image charge discharged from the second LOFIC compensate each other during a readout period.

    LOFIC circuit for in pixel metal-insulator-metal(MIM) capacitor lag correction and associated correction methods

    公开(公告)号:US12096141B2

    公开(公告)日:2024-09-17

    申请号:US18154715

    申请日:2023-01-13

    CPC classification number: H04N25/59 H01L27/14612 H01L27/14643 H04N25/771

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network is coupled between the reset transistor and a bias voltage source. The LOFIC network includes a main LOFIC coupled between the reset transistor and the bias voltage source, and a plurality of subordinate capacitor-switch pairs, each including a subordinate LOFIC and a switch transistor coupled to the subordinate LOFIC. Each of the plurality of subordinate capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.

    Suppressed cross-talk pixel-array substrate and fabrication method

    公开(公告)号:US12087792B2

    公开(公告)日:2024-09-10

    申请号:US17572413

    申请日:2022-01-10

    Abstract: A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region.

    HIGH K METAL-INSULATOR-METAL (MIM) CAPACITOR NETWORK FOR LAG MITIGATION

    公开(公告)号:US20240244350A1

    公开(公告)日:2024-07-18

    申请号:US18154770

    申请日:2023-01-13

    CPC classification number: H04N25/77

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor-switch pairs is coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor-switch pairs includes a lateral overflow integration capacitor (LOFIC) and a switch transistor coupled to the LOFIC.

    IMAGE SENSOR DIAGONAL ISOLATION STRUCTURES
    40.
    发明公开

    公开(公告)号:US20230307478A1

    公开(公告)日:2023-09-28

    申请号:US17705133

    申请日:2022-03-25

    CPC classification number: H01L27/1463 H01L27/14629

    Abstract: Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

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