公开(公告)号：US07042763B1

公开(公告)日：2006-05-09

申请号：US10895711

申请日：2004-07-08

Applicant: Yuri Mirgorodski ,  Pavel Poplevine ,  Peter J. Hopper ,  Andrew J. Franklin

Inventor： Yuri Mirgorodski ,  Pavel Poplevine ,  Peter J. Hopper ,  Andrew J. Franklin

IPC: G11C11/34

CPC classification number: G11C16/0441 ,  G11C2216/10

Abstract: A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.

Abstract translation: 一种选择性地编程非易失性存储单元的方法，其中使用多个编程电压来获得所选择用于编程的单元的存储节点上的期望电压，而未选定单元的存储节点保持不受干扰。

公开(公告)号：US06972995B1

公开(公告)日：2005-12-06

申请号：US10821391

申请日：2004-04-09

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Wendy Greig

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Wendy Greig

IPC: G11C16/04 ,  G11C16/10 ,  G11C27/00

CPC classification number: G11C27/005 ,  G11C16/10

Abstract: The image capture period of an imaging cell, or the total time that an imaging cell is exposed to light energy, is substantially increased by utilizing a non-volatile memory (NVM), such as an electrically-erasable, programmable, read-only-memory (EEPROM) structure. The NVM structure stores and integrates charges that are proportional to the absorbed photons over a large number of sequential integration periods.

Abstract translation: 成像单元的图像捕获周期或成像单元暴露于光能的总时间通过利用诸如电可擦除可编程的只读存储器之类的非易失性存储器（NVM）而显着增加， 存储器（EEPROM）结构。 NVM结构在大量的顺序集成周期内存储和积分与吸收的光子成比例的电荷。

公开(公告)号：US06972457B1

公开(公告)日：2005-12-06

申请号：US10821286

申请日：2004-04-09

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/146 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/14603 ,  H01L27/14609

Abstract: The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

Abstract translation: 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

公开(公告)号：US06964907B1

公开(公告)日：2005-11-15

申请号：US10716276

申请日：2003-11-17

Applicant: Peter J. Hopper ,  Alexei Sadovnikov ,  Vladislav Vashchenko ,  Peter Johnson

Inventor： Peter J. Hopper ,  Alexei Sadovnikov ,  Vladislav Vashchenko ,  Peter Johnson

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/331 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC classification number: H01L21/30608 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322

Abstract: In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.

Abstract translation: 在BJT中，通过在外部基极区域和集电极之间形成横向沟槽来减小外部基极到集电极电容。 这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。

公开(公告)号：US06956269B1

公开(公告)日：2005-10-18

申请号：US10744252

申请日：2003-12-22

Applicant: Vladislav Vashchenko ,  Michael Mian ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Michael Mian ,  Peter J. Hopper

IPC: H01L29/66 ,  H01L29/82

CPC classification number: H01L29/66984

Abstract: Spin-based microelectronic devices can be realized by utilizing spin-polarized ferromagnetic materials positioned near, or embedded in, a semiconductor channel of a microelectronic device. Applying an electric field across the channel can cause carriers flowing through the channel to deviate toward one of the ferromagnetic materials, such that the spin of the carriers tends to align with the spin polarization of the respective material. Such a process allows for the controlled spin-polarization of carriers in a semiconductor channel, and hence the development of spin-based microelectronics, without having to inject spin-polarized carriers from a ferromagnet into a semiconductor channel. Such a process avoids the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on silicon substrates that are well-known and used in the industry.

Abstract translation: 旋转微电子器件可以通过利用位于微电子器件的半导体通道附近或嵌入其中的自旋极化铁磁材料来实现。 通过通道施加电场可以使流过通道的载流子偏向铁磁材料之一，使得载流子的自旋倾向于与相应材料的自旋极化对准。 这种方法允许半导体通道中载流子的受控自旋极化，从而允许自旋基微电子学的发展，而不必将自旋极化载流子从铁磁体注入到半导体通道中。 这种过程避免了肖特基势垒问题困扰着现有的基于旋转微电子学的方法，同时允许器件基于业界众所周知和使用的硅衬底。

公开(公告)号：US06906357B1

公开(公告)日：2005-06-14

申请号：US10683625

申请日：2003-10-10

Applicant: Vladislav Vashchenko ,  Marcel ter Beek ,  Peter J. Hopper ,  Ann Concannon

Inventor： Vladislav Vashchenko ,  Marcel ter Beek ,  Peter J. Hopper ,  Ann Concannon

IPC: H01L27/02 ,  H01L29/72

CPC classification number: H01L27/0259

Abstract: An apparatus including an electrostatic discharge (ESD) protection structure with a diac in which substancially similar ESD protection is provided for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected.

Abstract translation: 一种包括具有diac的静电放电（ESD）保护结构的装置，其中为保护电路电极处出现的正和负ESD电压提供了基本相似的ESD保护。

公开(公告)号：US06903979B1

公开(公告)日：2005-06-07

申请号：US10664758

申请日：2003-09-17

Applicant: Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter J. Hopper ,  Douglas J. Brisbin

Inventor： Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter J. Hopper ,  Douglas J. Brisbin

IPC: G11C16/00 ,  G11C16/10

CPC classification number: G11C16/10

Abstract: A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.

Abstract translation: 提供了一种编程PMOS堆叠栅极存储单元的方法，其利用在编程周期期间的注入电流和衬底电流之间的相关性来向存储器单元的控制栅极提供反馈校正，以补偿浮置栅极上的负电位移位 作为其充电时间的结果。

公开(公告)号：US06838711B1

公开(公告)日：2005-01-04

申请号：US10658432

申请日：2003-09-08

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vludislav Vashchenko ,  Rob Drury

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vludislav Vashchenko ,  Rob Drury

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L27/10

CPC classification number: H01L29/4238 ,  H01L29/0692 ,  H01L29/78

Abstract: In a MOS array, current loss at distances further away from the drain and source contacts is compensated for by adjusting the length of the polygate. In an array with drain and source contacts near the middle of the structure, the length of the polygate tapers off along the width of the polygate towards both ends of the polygate.

Abstract translation: 在MOS阵列中，通过调整多晶硅栅极的长度来补偿远离漏极和源极触点的距离处的电流损耗。 在具有靠近结构中间的漏极和源极触点的阵列中，多晶硅栅极的长度沿着多晶硅的宽度朝着多晶硅的两端逐渐变细。

公开(公告)号：US06822294B1

公开(公告)日：2004-11-23

申请号：US09896681

申请日：2001-06-29

Applicant: Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper

IPC: H01L2362

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.

Abstract translation: 在使用类似LVTSCR的结构的ESD保护器件中，通过将p +发射极放置在器件的漏极之外，从而延长了p +发射极的空穴注入，从而提高了保持电压。 p +发射极可以在形成在漏极外部的一个或多个发射极区域中实现。 漏极在栅极附近的n +漏极和浮动n +区域之间分开，以避免过度的雪崩注入和局部过热。

公开(公告)号：US06806529B1

公开(公告)日：2004-10-19

申请号：US10356422

申请日：2003-01-30

Applicant: Peter J. Hopper ,  Yuri Mirgorodski ,  Andy Strachan

Inventor： Peter J. Hopper ,  Yuri Mirgorodski ,  Andy Strachan

IPC: H01L2972

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate, providing a cell with a high overall capacitive coupling ratio, a relatively small area, and a high voltage tolerance.

Abstract translation: 在电可编程非易失性存储单元中，高密度电容结构的第一端子电连接到导电结构以形成浮置栅极/第一电极，而电容结构的第二端子用作控制栅极， 提供具有高总体电容耦合比，相对小的面积和高电压容限的电池。