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    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    33.
    发明授权
    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
    单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US07283401B2

    公开(公告)日：2007-10-16

    申请号：US11391507

    申请日：2006-03-28

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04 ,  G11C5/06 ,  H01L29/76 ,  H01L23/544

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

    Set of three level concurrent word line bias conditions for a NOR type flash memory array
    35.
    发明授权
    Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
    用于NOR型闪存阵列的三级并发字线偏置条件集

    公开(公告)号：US06818491B2

    公开(公告)日：2004-11-16

    申请号：US10627834

    申请日：2003-07-25

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    IPC分类号： H01L218238

    CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

    摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

    摘要翻译： 在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。 第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。 第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。 此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。 三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。 本文描述的方法产生具有窄电压分布的电池阈值电压。

    Flash memory array structure suitable for multiple simultaneous operations
    36.
    发明授权
    Flash memory array structure suitable for multiple simultaneous operations 有权
    闪存阵列结构适用于多个同时操作

    公开(公告)号：US06788611B2

    公开(公告)日：2004-09-07

    申请号：US10423558

    申请日：2003-04-25

    申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

    发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

    IPC分类号： G11C800

    CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C8/12 ,  G11C2216/22

    摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

    摘要翻译： 在本发明中公开了一种用于同时读和写操作的闪速存储器。 存储器被划分成多个扇区，每个扇区具有扇区解码器。 扇区解码器将多个主位线连接到包含在每个存储器扇区中的多个子位线A 2解码器用于演示本发明，尽管包括2解码器和分层式解码器的其他解码器可以 使用。 存储器阵列可以由各种架构进行配置，包括NOR，OR，NAND，AND，Dual-String和DINOR。 存储器单元可以由包括ETOX，FLOTOX，EPROM，EEPROM，分离栅极和PMOS的各种阵列结构形成。

    Circuit design for accepting multiple input voltages for flash EEPROM memory operations
    37.
    发明授权
    Circuit design for accepting multiple input voltages for flash EEPROM memory operations 有权
    用于接受快速EEPROM存储器操作的多个输入电压的电路设计

    公开(公告)号：US06574152B1

    公开(公告)日：2003-06-03

    申请号：US10104736

    申请日：2002-03-22

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

    IPC分类号： G11C700

    CPC分类号： G11C16/30 ,  G11C2207/105 ,  G11C2207/2227

    摘要： In the present invention an EEPROM flash memory is operated using the I/O pins of an EPROM. A novel circuit is used that allows a plurality of voltages to be applied at different times to a single pin designated as CEB (chip enable bar) that permits reading and writing of the flash memory chip. The plurality of voltages can range from a positive voltage, to a ground voltage and to a negative voltage. When a positive voltage like Vdd is applied to the the CEB pin the chip is disabled and entered into a standby mode. When a ground voltage is applied to the CEB pin, the flash memory chip is enabled and a read operation can be performed. When a high negative voltage is applied to the CEB pin, the circuit of the present invention produces an internal high negative voltage to be used for a write operation.

    摘要翻译： 在本发明中，使用EPROM的I / O引脚来操作EEPROM闪速存储器。 使用一种新颖的电路，其允许在不同时间将多个电压施加到指定为允许读取和写入闪存芯片的CEB（芯片使能条）的单个引脚。 多个电压可以从正电压到接地电压和负电压的范围。 当Vdd等正电压施加到CEB引脚时，芯片被禁止并进入待机模式。 当接地电压施加到CEB引脚时，闪存芯片被使能，并且可以执行读操作。 当向CEB引脚施加高负电压时，本发明的电路产生用于写入操作的内部高负电压。

    Erase condition for flash memory
    38.
    发明授权
    Erase condition for flash memory 有权
    擦除闪存的条件

    公开(公告)号：US6134150A

    公开(公告)日：2000-10-17

    申请号：US360315

    申请日：1999-07-23

    申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Vei-Han Chan ,  Hung-Sheng Chen

    发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Vei-Han Chan ,  Hung-Sheng Chen

    IPC分类号： G11C16/14 ,  G11C7/00

    CPC分类号： G11C16/14

    摘要： In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.

    摘要翻译： 在本发明中，公开了一种闪存配置，其不需要通常需要两个泵电路之一来支持闪存芯片上的存储器单元的擦除功能。 将闪存单元置于三阱结构中，其中P阱包含在驻留在P基底上的深N阱内。 选择用于擦除闪存单元的偏置电压，以便仅需要将一个电压泵电路包括在闪存芯片中。 芯片偏置VDD用于存储单元的源极，负栅极电压上升幅度以保持擦除操作的效率。 P阱被施加负电压，该负电压足以防止连接到栅极的高负电压引起字线解码器电路中的击穿。 深N阱和P衬底被偏置，以便反向偏置三阱结构之间的P / N结。

    Positive/negative high voltage charge pump system
    39.
    发明授权
    Positive/negative high voltage charge pump system 有权
    正/负高压电荷泵系统

    公开(公告)号：US6023188A

    公开(公告)日：2000-02-08

    申请号：US232115

    申请日：1999-01-15

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

    IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C11/56 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  H02M3/07 ,  G05F3/02

    CPC分类号： G05F3/20 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H02M3/073

    摘要： A two-phase high voltage generator circuit is electronically reconfigurable to output positive (V.sub.Pp) or negative (V.sub.Pn) high voltage, depending upon whether positive or negative mode operation is selected. The circuit includes a plurality of series-connected charge multiplier stages that each comprises a MOS transistor and a charging capacitor. Collectively the stages define an anode node and a cathode node. One of two non-overlapping phase signals is coupled to the free end of each charging capacitor such that adjacent charging capacitors are driven by different phases. First and second two-way multiplexers (MUX1, MUX2) control voltages presented to the anode and cathode nodes, to determine whether circuit operation is positive or negative mode. The MOS devices may be PMOS or NMOS, and preferably Vt-cancellation is provided for each charging stage. A precharge/discharge circuit preferably is coupled to each voltage node including the load capacitor. Further, substrate-well protection is provided such that the MOS devices are less prone to exhibit voltage breakdown or substrate to source/drain current flow.

    摘要翻译： 根据是选择正还是负模式操作，两相高压发生器电路是电子可重新配置的，以输出正（VPp）或负（VPn）高电压。 电路包括多个串联连接的电荷倍增器级，每个级包括MOS晶体管和充电电容器。 这些阶段总共定义了阳极节点和阴极节点。 两个非重叠相位信号中的一个耦合到每个充电电容器的自由端，使得相邻的充电电容器由不同的相位驱动。 第一和第二双向多路复用器（MUX1，MUX2）提供给阳极和阴极节点的控制电压，以确定电路操作是正还是负模式。 MOS器件可以是PMOS或NMOS，并且优选地为每个充电阶段提供Vt消除。 预充电/放电电路优选地耦合到包括负载电容器的每个电压节点。 此外，提供衬底井保护，使得MOS器件不太容易出现电压击穿或衬底到源极/漏极电流。

    Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices
    40.
    发明授权
    Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices 失效
    使用薄氧化物和厚氧化物半导体器件的高速擦除结构的闪存

    公开(公告)号：US5914896A

    公开(公告)日：1999-06-22

    申请号：US915344

    申请日：1997-08-22

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

    IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/00

    CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3431 ,  H01L27/115 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5645 ,  G11C8/00 ,  G11C8/14

    摘要： A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. In another second embodiment, the wordline decoder is constructed from thin oxide and thick oxide semiconductor devices. Thick oxide devices are used in the wordline driver, which allows an increased voltage differential to be applied to the wordlines without damaging the wordline driver. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to be erased.

    摘要翻译： 具有高速擦除结构的闪速存储器包括具有多个字线的组闪存晶体管，多个位线和源极线。 字线解码器耦合到字线并且被配置为选择性地向字线施加电压以对闪存晶体管执行过程，其中过程包括读取过程，擦除过程和程序过程。 在擦除过程期间，字线解码器被配置为将第一电压范围中的第一越来越大的负电压施加到至少一个选定字线，直到满足第一阈值电压，然后在第二电压范围内施加第二越来越大的负电压， 并且将第三电压范围中的第三负电压同时施加到至少一个取消选择的字线。 本发明的另一实施例增加了所选择的源极线电压，以实现选择被擦除的闪光晶体管的栅极和源极之间的高电压差。 在另一第二实施例中，字线解码器由薄氧化物和厚氧化物半导体器件构成。 在字线驱动器中使用厚的氧化物装置，这允许将增加的电压差施加到字线而不损害字线驱动器。 本发明的优点包括快速擦除程序，这是由于在被选择被擦除的闪光晶体管的栅极和源极之间施加的电压差增大。