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    FUEL CELL APPARATUS AND ASSOCIATED METHOD
    31.
    发明申请
    FUEL CELL APPARATUS AND ASSOCIATED METHOD 失效
    燃料电池装置及相关方法

    公开(公告)号：US20070141415A1

    公开(公告)日：2007-06-21

    申请号：US11566347

    申请日：2006-12-04

    申请人： Hai Yang ,  Chang Wei ,  Qunjian Huang ,  Jinghua Liu ,  Rihua Xiong ,  Jun Cai ,  Shengxian Wang

    发明人： Hai Yang ,  Chang Wei ,  Qunjian Huang ,  Jinghua Liu ,  Rihua Xiong ,  Jun Cai ,  Shengxian Wang

    IPC分类号： H01M8/04 ,  H01M4/96 ,  H01M8/06 ,  H01M4/90

    CPC分类号： H01M12/005 ,  H01G9/08 ,  H01G9/155 ,  H01M8/04119 ,  H01M8/04216 ,  H01M8/18 ,  H01M12/06 ,  Y02E60/13

    摘要： An apparatus including a housing having walls is provided. The walls of the housing each have inner surfaces and outer surfaces. The walls may include apertures extending from the inner surface to the outer surface. The inner surfaces of the walls define a volume. The volume includes an electrode. The volume further includes a water-controlling separator disposed between the inner surface of the housing and the electrode. The water-controlling separator can block a flow of liquid from the electrode through the apertures to the ambient environment while allowing oxidant to flow from the ambient environment through the apertures to the electrode.

    摘要翻译： 提供一种包括具有壁的壳体的装置。 壳体的壁各自具有内表面和外表面。 壁可以包括从内表面延伸到外表面的孔。 壁的内表面定义一个体积。 体积包括电极。 体积还包括设置在壳体的内表面和电极之间的防水分离器。 水控制分离器可以阻止液体从电极通过孔流到周围环境，同时允许氧化剂从周围环境通过孔流动到电极。

    HIGH-VOLTAGE DIODES FORMED IN ADVANCED POWER INTEGRATED CIRCUIT DEVICES
    32.
    发明申请
    HIGH-VOLTAGE DIODES FORMED IN ADVANCED POWER INTEGRATED CIRCUIT DEVICES 有权
    高功率集成电路器件中形成的高压二极管

    公开(公告)号：US20060118814A1

    公开(公告)日：2006-06-08

    申请号：US11005755

    申请日：2004-12-07

    申请人： Jun Cai ,  Micheal Harley-Stead ,  Jim Holt

    发明人： Jun Cai ,  Micheal Harley-Stead ,  Jim Holt

    IPC分类号： H01L29/43

    CPC分类号： H01L29/861 ,  H01L29/7391

    摘要： A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

    摘要翻译： 在第一导电类型的衬底上的二极管连接的横向晶体管包括垂直寄生晶体管，寄生衬底漏电流通过该垂直寄生晶体管流动。 提供了用于分流远离垂直寄生晶体管的寄生衬底泄漏电流的至少一部分的装置。

    ESD protection for semiconductor products
    33.
    发明申请
    ESD protection for semiconductor products 有权
    半导体产品的ESD保护

    公开(公告)号：US20050148124A1

    公开(公告)日：2005-07-07

    申请号：US11054189

    申请日：2005-02-09

    申请人： Jun Cai ,  Alvin Sugerman ,  Steven Park

    发明人： Jun Cai ,  Alvin Sugerman ,  Steven Park

    IPC分类号： H01L20060101 ,  H01L21/338 ,  H01L23/62 ,  H01L27/02 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7833 ,  H01L27/0266

    摘要： A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.

    摘要翻译： 用于形成具有用于承载击穿电流的ESD保护晶体管的垂直DMOS器件的工艺包括以下步骤：掩蔽第一极性类型的衬底并形成间隔开的表面隔离区域。 在间隔开的表面隔离区域之间形成绝缘栅极。 在栅极和表面隔离区域之间的表面区域的选定部分被杂散以形成在衬底表面下方具有逆向掺杂分布的pn结，从而降低异质部分之下的击穿电压，以将击穿电流的大部分引导到低于 衬底的表面并进入到异质区域之间的衬底的主体中。 源极和漏极区域形成在栅极的相对侧上的衬底表面中。

    ESD parasitic bipolar transistors with high resistivity regions in the collector
    34.
    发明授权
    ESD parasitic bipolar transistors with high resistivity regions in the collector 有权
    集电极中具有高电阻率区域的ESD寄生双极晶体管

    公开(公告)号：US06787880B2

    公开(公告)日：2004-09-07

    申请号：US10437093

    申请日：2003-05-13

    申请人： David Hu ,  Jun Cai

    发明人： David Hu ,  Jun Cai

    IPC分类号： H01L218238

    CPC分类号： H01L27/027

    摘要： A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.

    摘要翻译： 一种在寄生NPN的集电极内具有高电阻率区域的寄生双极硅化ESD器件的方法和结构。 该器件具有N-MOS晶体管和衬底接触的结构。 器件优选在掺杂区域上方具有硅化物区域。 本发明具有两种类型的高电阻率区域：1）隔离区域（例如，氧化物浅沟槽隔离（STI））和2）未掺杂或轻掺杂区域（例如沟道区）。 通道区域可以有栅极，栅极可以充电。 此外，可以在收集器下方形成任选的n - 阱（n-negative well）。 高电阻率区域增加了集电极电阻率，从而提高了寄生双极型ESD器件的性能。

    Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks
    35.
    发明授权
    Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks 有权
    低触发N MOS晶体管用于在没有硅化物块的完全硅化工艺下工作的ESD保护

    公开(公告)号：US06444510B1

    公开(公告)日：2002-09-03

    申请号：US09999246

    申请日：2001-12-03

    申请人： David Hu ,  Jun Cai

    发明人： David Hu ,  Jun Cai

    IPC分类号： H01L21336

    CPC分类号： H01L29/0847 ,  H01L27/0259 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/735 ,  H01L29/7835

    摘要： An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n− well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region. The third n+ region is preferably shorted (or connected) to the first p+ region and the second n+ region. The third embodiment forms a second NPN parasitic bipolar using the third N+ region as an emitter. The forth embodiment contains the same elements as the third embodiment with the addition of a second gate over the first isolation region. The second gate is preferably connected to the third n+ region to the first p+ region and the second n+ region. The gate changes the electrical characteristics of the first parasitic bipolar transistor.

    摘要翻译： 使用硅化的寄生双极晶体管的ESD器件和方法。 第一实施例是由n + / n- / p- / n- / n +区组成的寄生双极结晶体管。 发射极由第二N +区和第二N-阱构成。 寄生基底由p-基底或阱形成。 集电极由第一阱和第一n +区形成。 第一实施例的好处是触发电压较低，因为n阱（发射极）与P-衬底（基极）之间的结以及P-衬底（基极）与n-阱之间的结有较低的交叉浓度 。 第二实施例与第一实施例类似，附加第一门。 第一栅极优选地连接到第一n +区域和Vpad。 第三实施例包含与第二实施例相同的元件，并添加第三n +区。 第三n +区域优选地与第一p +区域和第二n +区域短接（或连接）。 第三实施例使用第三N +区域作为发射器形成第二NPN寄生双极。 第四实施例包含与第三实施例相同的元件，在第一隔离区域上添加第二栅极。 第二栅极优选地连接到第三n +区到第一p +区和第二n +区。 门改变第一寄生双极晶体管的电特性。

    Method of making polymeric barrier coating to mitigate binder migration in a diesel particulate filter to reduce filter pressure drop and temperature gradients
    37.
    发明授权
    Method of making polymeric barrier coating to mitigate binder migration in a diesel particulate filter to reduce filter pressure drop and temperature gradients 有权
    制造聚合物阻隔涂层以减轻柴油颗粒过滤器中的粘合剂迁移以减少过滤器压降和温度梯度的方法

    公开(公告)号：US09593608B2

    公开(公告)日：2017-03-14

    申请号：US13509480

    申请日：2011-01-03

    申请人： Jun Cai ,  Steven J. Martin

    发明人： Jun Cai ,  Steven J. Martin

    IPC分类号： C04B35/00 ,  F01N3/022 ,  C04B35/626 ,  C04B35/634 ,  C04B35/636 ,  C04B37/00 ,  C04B38/00 ,  C04B111/00

    CPC分类号： F01N3/0222 ,  C04B35/6263 ,  C04B35/63488 ,  C04B35/6365 ,  C04B37/005 ,  C04B38/0019 ,  C04B2111/00793 ,  C04B2235/5228 ,  C04B2235/96 ,  C04B2237/062 ,  C04B2237/064 ,  C04B2237/10 ,  C04B2237/341 ,  Y02T10/20 ,  Y10T428/24149 ,  C04B35/00 ,  C04B38/0012

    摘要： Ceramic honeycomb structures and methods to make the same are disclosed. The structures may be comprised of at least two separate smaller ceramic honeycombs that have been coated with a polymer to create a polymeric barrier coating and adhered together with a cement comprised of inorganic fibers and a binding phase which is comprised of amorphous silicate, aluminite or alumino silicate glass and other inorganic particles. The polymer is selected such that it is penetratable into or covering the pores in the honeycomb structure to form a thin barrier layer thereon to mitigate migration of the inorganic fibers, binding phase and water into the pores. The polymer is adapted to be burned off or decomposed at or below cement and honeycomb skin firing temperatures, or at or below honeycomb operating temperatures during application to create a honeycomb structure that, when formed into an exhaust filter, does not have any undesired pressure drop increase due to cement migration.

    摘要翻译： 公开了陶瓷蜂窝结构体及其制造方法。 结构可以由至少两个单独的较小的陶瓷蜂窝组成，其已经被聚合物涂覆以产生聚合物阻挡涂层并且与由无机纤维组成的粘合剂和由无定形硅酸盐，铝酸盐或铝制成的结合相粘合在一起 硅酸盐玻璃等无机颗粒。 选择聚合物使得其可渗透入蜂窝结构中的孔或覆盖蜂窝状结构中的孔，以在其上形成薄的阻挡层，以减轻无机纤维的迁移，将相结合和水结合到孔中。 该聚合物适于在施用期间在水泥和蜂窝状皮肤焙烧温度下或在蜂窝状工作温度以下或低于蜂窝状的工作温度下燃烧或分解，以形成蜂窝状结构，当形成排气过滤器时，其不具有任何不期望的压降 由于水泥迁移而增加。

    Two low complexity decoding algorithms for LDPC codes
    40.
    发明授权
    Two low complexity decoding algorithms for LDPC codes 有权
    LDPC码的两种低复杂度解码算法

    公开(公告)号：US08972817B2

    公开(公告)日：2015-03-03

    申请号：US13486077

    申请日：2012-06-01

    申请人： Telex Maglorie Ngatched Nkouatchah ,  Attahiru Sule Alfa ,  Jun Cai

    发明人： Telex Maglorie Ngatched Nkouatchah ,  Attahiru Sule Alfa ,  Jun Cai

    IPC分类号： H03M13/00 ,  G06F11/00 ,  H03M13/11

    CPC分类号： H03M13/6527 ,  H03M13/1117 ,  H03M13/1165 ,  H03M13/6544 ,  H03M13/6577 ,  H03M13/658

    摘要： In the present invention, two improved variants of the reliability-based iterative majority-logic decoding algorithm for regular low-density parity-check (LDPC) codes are presented. The new algorithms are obtained by introducing a different reliability measure for each check-sum of the parity-check matrix, and taking it into account in the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration. In contrast to the first algorithm, the second algorithm includes check reliability that changes at each iteration. For the tested random and structured LDPC codes, both algorithms, while requiring very little additional computational complexities, achieve a considerable error performance gain over the standard one. More importantly, for short and medium block length LDPC codes of relatively large column weight, both algorithms outperform or perform just as well as the iterative decoding based on belief propagation (IDBP) with less decoding complexity.

    摘要翻译： 在本发明中，提出了用于常规低密度奇偶校验（LDPC）码的基于可靠性的迭代多数逻辑解码算法的两个改进的变体。 通过对奇偶校验矩阵的每个校验和引入不同的可靠性度量来获得新算法，并且在用于更新每个迭代中每个接收比特的可靠性度量的外在信息的计算中考虑 。 与第一种算法相反，第二种算法包括在每次迭代时改变的校验可靠性。 对于测试的随机和结构化LDPC码，这两种算法在需要非常少的额外的计算复杂性的情况下实现了比标准算法更大的错误性能增益。 更重要的是，对于相对较大的列权重的短和中块长度的LDPC码，两种算法比基于具有较低解码复杂度的置信传播（IDBP）的迭代解码性能优于或执行。