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公开(公告)号：US20100151152A1
公开(公告)日：2010-06-17
申请号：US12700395
申请日：2010-02-04
CPC分类号： G02B5/286 , Y10T428/259
摘要： A non-stoichiometric SiOXNY thin-film optical filter is provided. The filter is formed from a substrate and a first non-stoichiometric SiOX1NY1 thin-film overlying the substrate, where (X1+Y1 0). The first non-stoichiometric SiOX1NY1 thin-film has a refractive index (n1) in the range of about 1.46 to 3, and complex refractive index (N1=n1+ik1), where k1 is an extinction coefficient in a range of about 0 to 0.5. The first non-stoichiometric SiOX1NY1 thin-film may be either intrinsic or doped. In one aspect, the first non-stoichiometric SiOX1NY1 thin-film has nanoparticles with a size in the range of about 1 to 10 nm. A second non-stoichiometric SiOX2NY2 thin-film may overlie the first non-stoichiometric SiOX1NY1 thin-film, where Y1≠Y2. The second non-stoichiometric SiOX1NY1 thin-film may be intrinsic and doped. In another variation, a stoichiometric SiOX2NY2 thin-film, intrinsic or doped, overlies the first non-stoichiometric SiOX1NY1 thin-film.
摘要翻译： 提供非化学计量的SiOXNY薄膜滤光片。 滤光片由衬底和覆盖衬底的第一非化学计量的SiOX1NY1薄膜形成，其中（X1 + Y1 <2和Y1> 0）。 第一非化学计量的SiOX1NY1薄膜的折射率（n1）在约1.46至3的范围内，复数折射率（N1 = n1 + ik1），其中k1是约0至 0.5。 第一非化学计量的SiOX1NY1薄膜可以是固有的或掺杂的。 在一个方面，第一非化学计量的SiOX1NY1薄膜具有尺寸在约1至10nm范围内的纳米颗粒。 第二非化学计量的SiOX2NY2薄膜可以覆盖第一非化学计量的SiOX1NY1薄膜，其中Y1≠Y2。 第二非化学计量的SiOX1NY1薄膜可以是固有的和掺杂的。 在另一个实施方案中，本征或掺杂的化学计量的SiOX2NY2薄膜覆盖在第一非化学计量的SiOX1NY1薄膜上。
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公开(公告)号：US07157737B2
公开(公告)日：2007-01-02
申请号：US11101741
申请日：2005-04-07
IPC分类号： H01L29/04
摘要： Single-crystal devices and a method for forming semiconductor film single-crystal domains are provided. The method comprises: forming a substrate, such as glass or Si; forming an insulator film overlying the substrate; forming a single-crystal seed overlying the substrate and insulator; forming an amorphous film overlying the seed; annealing the amorphous film; and, forming a single-crystal domain in the film responsive to the single-crystal seed. The annealing technique can be (conventional) laser annealing, a laser induced lateral growth (LiLAC) process, or conventional furnace annealing. In some aspects, forming a single-crystal seed includes forming a nanowire or a self assembled monolayer (SAM). For example, a Si nanowire can be formed having a crystallographic orientation of or . When, the seed has a crystallographic orientation, then an n-type TFT can be formed. Likewise, when a single-crystal seed has a crystallographic orientation, a p-type TFT can be formed.
摘要翻译： 提供单晶器件和形成半导体膜单晶畴的方法。 该方法包括：形成诸如玻璃或Si的衬底; 形成覆盖在基板上的绝缘膜; 形成覆盖衬底和绝缘体的单晶种子; 形成覆盖种子的无定形膜; 退火非晶膜; 并且响应于单晶种子在膜中形成单晶畴。 退火技术可以是（常规）激光退火，激光诱导横向生长（LiLAC）工艺或常规炉退火。 在一些方面，形成单晶种子包括形成纳米线或自组装单层（SAM）。 例如，可以形成具有<110>或<100>的晶体取向的Si纳米线。 当种子具有<100>晶体取向时，则可以形成n型TFT。 同样，当单晶种子具有<110>结晶取向时，可以形成p型TFT。
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公开(公告)号：US07569410B2
公开(公告)日：2009-08-04
申请号：US11640592
申请日：2006-12-18
IPC分类号： H01L21/00
CPC分类号： B81C1/0023 , H01L27/1214
摘要： An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.
摘要翻译： 提供集成MEMS封装和相关封装方法。 该方法包括：形成电连接到第一基板的电路; 将MEMS器件集成在电连接到第一衬底的第一衬底区域上; 提供覆盖所述第一基板的第二基板; 以及沿所述第一区域边界在所述第一和第二基板之间形成壁。 在一个方面，使用薄膜工艺形成电路; 并且其中将MEMS器件集成在第一衬底区域上包括使用薄膜工艺形成MEMS，同时形成电子器件。 或者，MEMS器件以独立的工艺形成，附接到第一衬底，并且使用薄膜工艺将电互连形成到第一衬底。
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公开(公告)号：US07431766B2
公开(公告)日：2008-10-07
申请号：US11227843
申请日：2005-09-14
申请人： John W. Hartzell
发明人： John W. Hartzell
IPC分类号： C30B19/10
摘要： Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, mechanical devices. Processing is laser-performed in relation to a selected material whose internal crystalline structure becomes appropriately changed thereby to establish the desired mechanical properties for a created device.
摘要翻译： 加工和系统创建，以及与之相关的产品，非常小尺寸的奇异或单片阵列的机械装置。 相对于其内部晶体结构变得适当变化的选定材料进行激光处理，从而建立所创造的器件的期望的机械性能。
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公开(公告)号：US07306962B2
公开(公告)日：2007-12-11
申请号：US10871938
申请日：2004-06-17
申请人： David R. Evans , John W. Hartzell
发明人： David R. Evans , John W. Hartzell
IPC分类号： H01L21/00
CPC分类号： H01L21/288 , C23C18/1605 , C23C18/165 , C23C18/1657 , C25D1/003 , C25D5/022 , C25D5/50 , H01L21/2885 , H01L21/76885
摘要： A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
摘要翻译： 提供了一种电铸金属集成电路结构的方法。 该方法包括：通过层间绝缘体形成诸如通孔或线的开口，暴露衬底表面; 形成覆盖层间绝缘体和衬底表面的基层; 形成覆盖基层的冲击层; 形成覆盖所述冲击层的顶层; 选择性蚀刻以去除覆盖在衬底表面上的顶层，暴露出一层击打层表面; 并且电铸在覆盖着撞击层表面的金属结构。 使用电镀或无电沉积工艺沉积电铸金属结构。 通常，金属是Cu，Au，Ir，Ru，Rh，Pd，Os，Pt或Ag。 可以使用物理气相沉积（PVD），蒸发，反应溅射或金属有机化学气相沉积（MOCVD）来沉积基底，打击和顶层。
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公开(公告)号：US07230306B2
公开(公告)日：2007-06-12
申请号：US11058501
申请日：2005-02-14
申请人： John W. Hartzell
发明人： John W. Hartzell
IPC分类号： H01L29/84
摘要： Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, semiconductor mechanical devices. Processing is laser performed on selected semiconductor material whose internal crystalline structure becomes appropriately changed to establish the desired mechanical properties for a created device.
摘要翻译： 加工和制造系统，以及与之相关的产品，非常小尺寸的奇异或单片阵列的半导体机械装置。 对选择的半导体材料进行激光处理，该半导体材料的内部晶体结构被适当地改变以建立所需的机械性能。
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公开(公告)号：US20100276776A1
公开(公告)日：2010-11-04
申请号：US12434118
申请日：2009-05-01
申请人： Jong-Jan Lee , Steven R. Droes , John W. Hartzell , Jer-Shen Maa
发明人： Jong-Jan Lee , Steven R. Droes , John W. Hartzell , Jer-Shen Maa
IPC分类号： H01L31/028 , H01L21/02 , H01L31/0216
CPC分类号： H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14689 , H01L27/1469 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/351 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.
摘要翻译： 玻璃基板上的锗（Ge）光电二极管阵列具有相应的制造方法。 提供未掺杂或轻掺杂第一掺杂剂的Ge衬底。 第一掺杂剂可以是n型或p型掺杂剂。 Ge衬底的第一表面适度地掺杂有第一掺杂剂并且结合到玻璃衬底顶表面。 然后，Ge衬底第二表面的第一区域被第一掺杂剂重掺杂。 Ge衬底第二表面的第二区域重掺杂有与第一掺杂剂相反的电子亲和力的第二掺杂剂，形成pn结。 在Ge衬底第二表面上形成层间电介质（ILD）层，并且在覆盖Ge衬底第二表面的第一和第二区域的ILD层中蚀刻接触孔。 接触孔填充有金属，并且金属垫形成在接触孔上。
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公开(公告)号：US07785912B2
公开(公告)日：2010-08-31
申请号：US11818716
申请日：2007-06-15
IPC分类号： H01L21/00
CPC分类号： B81B3/0021 , B81B2201/0292 , B81B2203/0118 , B81C1/00246 , B81C2203/075 , C30B1/02 , C30B29/00 , G01L1/044 , G01L9/0042 , G01P15/0802 , G01P15/124 , G01P2015/0828 , H01L27/12 , H01L29/66757 , H04R17/02 , H04R31/006
摘要： A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.
摘要翻译： 提供了压电TFT悬臂微机电系统（MEMS）及相关制造工艺。 该方法包括：提供例如玻璃等基板; 形成覆盖衬底的薄膜; 形成薄膜悬臂梁; 并且同时在悬臂梁内形成TFT。 TFT可以形成为最少部分地覆盖在悬臂梁顶表面上，至少部分地覆盖悬臂梁底表面或嵌入在悬臂梁内。 在一个示例中，在衬底上形成薄膜包括：选择性地形成具有第一应力水平的第一层; 选择性地形成覆盖在第一层上的第一有源Si区; 以及以第二应力水平选择性地形成覆盖所述第一层的第二层。 薄膜悬臂梁由第一和第二层形成，而TFT源极/漏极（S / D）和沟道区域由第一有源Si区形成。
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公开(公告)号：US20100197065A1
公开(公告)日：2010-08-05
申请号：US12758879
申请日：2010-04-13
IPC分类号： H01L21/329
CPC分类号： B81B3/0021 , H01L29/868
摘要： A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.
摘要翻译： 提供压电薄膜二极管（压电二极管）悬臂微机电系统（MEMS）及相关制造工艺。 该方法沉积覆盖在基底上的薄膜。 基板可以由玻璃，聚合物，石英，金属箔，Si，蓝宝石，陶瓷或化合物半导体材料制成。 非晶硅（a-Si），多晶Si（poly-Si），氧化物，a-SiGe，poly-SiGe，金属，含金属的化合物，氮化物，聚合物，陶瓷膜，磁性膜和化合物半导体材料是一些例子 的薄膜材料。 悬臂梁由薄膜形成，二极管嵌入悬臂梁。 二极管由与悬臂梁共用的薄膜制成。 共享的薄膜可以是覆盖悬臂梁顶表面的薄膜，覆盖悬臂梁底表面的薄膜或嵌入在悬臂梁内的薄膜。
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公开(公告)号：US07682948B2
公开(公告)日：2010-03-23
申请号：US11483431
申请日：2006-07-10
申请人： John W. Hartzell
发明人： John W. Hartzell
IPC分类号： H01L21/20
CPC分类号： H01L21/02678 , B23K26/0604 , B23K26/0608 , B23K26/066 , H01L21/2026
摘要： A system and method are provided for crystallizing a semiconductor film using a digital light valve. The method comprises: enabling pixel elements from an array of selectable pixel elements; in response to enabling the pixel elements, gating a light; sequentially exposing adjacent areas of a semiconductor film, such as Si, to the gated light; annealing the light-exposed areas of semiconductor film; and, in response to the annealing, laterally growing crystal grains in the semiconductor film. For example, the method may sequentially expose adjacent areas of semiconductor film to gated light in a first direction; and, simultaneously exposing adjacent areas of semiconductor film to gated light in a second direction, different than the first direction. For example, the second direction may be perpendicular to the first direction. As a result, crystal grains can be laterally grown simultaneously in the first and second directions.
摘要翻译： 提供一种用于使用数字光阀使半导体膜结晶的系统和方法。 该方法包括：使可选像素元件阵列中的像素元件能够实现; 响应于使能像素元件，选择光; 将诸如Si的半导体膜的相邻区域依次曝光到门控光; 退火半导体膜的曝光区域; 并且响应于退火，在半导体膜中横向生长晶粒。 例如，该方法可以顺序地将半导体膜的相邻区域沿第一方向暴露于门控光; 并且同时将相邻的半导体膜区域暴露于与第一方向不同的第二方向的门控光。 例如，第二方向可以垂直于第一方向。 结果，晶粒可以在第一和第二方向上同时横向生长。
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