公开(公告)号：US20150115473A1

公开(公告)日：2015-04-30

申请号：US14064944

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri Narayan MOJUMDER

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/29 ,  H01L21/76251 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/528 ,  H01L24/83 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/267 ,  H01L2224/83948 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.

Abstract translation: 将异质沟道材料集成到半导体器件中的方法以及集成异构沟道材料的半导体器件。 一种制造半导体器件的方法包括以第一热预算处理第一材料的第一衬底以制造p型器件。 该方法还包括将第二材料的第二衬底耦合到第一衬底。 该方法还包括处理第二基板以在小于第一热预算的第二热预算下制造n型装置。 p型设备和n型设备可以协作以形成互补设备。

公开(公告)号：US20220415808A1

公开(公告)日：2022-12-29

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US20220344249A1

公开(公告)日：2022-10-27

申请号：US17242083

申请日：2021-04-27

Applicant: QUALCOMM Incorporated

Inventor： Biancun XIE ,  Shree Krishna PANDEY ,  Irfan KHAN ,  Miguel MIRANDA CORBALAN ,  Stanley Seungchul SONG

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

公开(公告)号：US20220022315A1

公开(公告)日：2022-01-20

申请号：US16929004

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jonghae KIM ,  Periannan CHIDAMBARAM

IPC: H05K1/11 ,  G06F1/18 ,  H05K1/02 ,  H05K3/10 ,  H05K3/40

Abstract: An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.

公开(公告)号：US20210375747A1

公开(公告)日：2021-12-02

申请号：US16889645

申请日：2020-06-01

Applicant: QUALCOMM Incorporated

Inventor： Ramesh MANCHANA ,  Sudheer Chowdary GALI ,  Biswa Ranjan PANDA ,  Dhaval SEJPAL ,  Stanley Seungchul SONG

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n≥4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.

公开(公告)号：US20200049757A1

公开(公告)日：2020-02-13

申请号：US16186623

申请日：2018-11-12

Applicant: QUALCOMM Incorporated

Inventor： Hyunwoo PARK ,  Youn Sung CHOI ,  Stanley Seungchul SONG

IPC: G01R31/26

Abstract: Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.

公开(公告)号：US20160314235A1

公开(公告)日：2016-10-27

申请号：US14693690

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F7/70433 ,  G06F17/5068 ,  G06F17/5081 ,  H01L27/0207

Abstract: A circuit layout data has a start value of a first-axis pitch and a start value of a second-axis pitch, the second axis pitch being transverse to the first-axis pitch. The start value of the first axis pitch and the start value of the second axis pitch correspond to single pattern lithography. The first axis pitch is scaled to a first axis single pattern-to-double pattern pitch transition threshold, and then additionally scaled until reaching a first axis double pattern resolution limit. Scaling the first axis pitch to the first axis double pattern resolution limit utilizes routing spaces parallel to the second axis pitch.

Abstract translation: 电路布局数据具有第一轴节距的起始值和第二轴节距的起始值，第二轴节距横向于第一轴节距。 第一轴距的开始值和第二轴距的开始值对应于单模式光刻。 第一轴音调被缩放到第一轴单一图案到双重图案间距转换阈值，然后另外缩放直到达到第一轴双重图案分辨率极限。 将第一轴距调整为第一轴双重图案分辨率极限利用与第二轴距平行的路线空间。

公开(公告)号：US20160284595A1

公开(公告)日：2016-09-29

申请号：US14670314

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Chunqi GENG ,  Choh Fei YEAP ,  Stanley Seungchul SONG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor chip includes a circuit block. The circuit block includes a first transistor(s) having an enhanced first performance characteristic different from a second performance characteristic of a second transistor(s) of the circuit block. The circuit block also includes a marker layer to identify the first transistor(s).

Abstract translation: 半导体芯片包括电路块。 电路块包括具有与电路块的第二晶体管的第二性能特性不同的增强的第一性能特性的第一晶体管。 电路块还包括标识层以识别第一晶体管。

公开(公告)号：US20160211216A1

公开(公告)日：2016-07-21

申请号：US14819159

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing BAO ,  John Jianhong ZHU ,  Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Choh Fei YEAP

IPC: H01L23/532 ,  G05B19/418 ,  H01L21/768 ,  B29C67/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

Abstract translation: 集成电路器件包括包括铝的第一金属层。 集成电路器件包括具有互连结构的第二金属层。 互连结构包括一层包括铝的第一材料。 集成电路器件包括包括铝的互扩散层。 互扩散层靠近第一金属层并且靠近包括铝的第一材料层。 集成电路器件包括包含铝的自形成阻挡层。 自形成阻挡层靠近电介质层并且靠近包括铝的第一材料层。

公开(公告)号：US20160181161A1

公开(公告)日：2016-06-23

申请号：US14581244

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7851

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active potion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract translation: 鳍状结构可以包括半导体衬底的表面上的翅片。 每个翅片可以包括靠近半导体衬底的表面的掺杂部分。 鳍状结构还可以包括设置在散热片之间和半导体衬底的表面上的隔离层。 鳍状结构还可以包括在散热片的掺杂部分的侧壁上的凹陷的隔离衬垫。 翅片的无衬里的掺杂部分可以从凹入的隔离衬垫延伸到隔离层的表面处的翅片的活性部分。 隔离层设置在翅片的无衬里的掺杂部分上。