公开(公告)号：US10599442B2

公开(公告)日：2020-03-24

申请号：US15448232

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Dhamim Packer Ali ,  Yanru Li ,  Ashutosh Shrivastava ,  Azzedine Touzni ,  Mamta Desai

IPC: G06F9/4401

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

公开(公告)号：US20190065752A1

公开(公告)日：2019-02-28

申请号：US16107956

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Chun

IPC: G06F21/57 ,  G06F1/32 ,  G06F15/78

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.

公开(公告)号：US20190006001A1

公开(公告)日：2019-01-03

申请号：US15636565

申请日：2017-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  Yanru Li

IPC: G11C11/406

Abstract: Systems and methods are disclosed for error correction control (ECC) for a refreshable memory device coupled to a system on a chip SoC. The memory device including a parity region and a user data region. A method includes determining with the SoC a first refresh rate for the user data region of the memory device and a second refresh rate for the parity region of the memory device, where the second refresh rate is different than the first refresh rate. Parity data is generated for a write operation of a user payload data (UPD) to the user data region of the memory device. The user data region of the memory device is refreshed at the first refresh rate and the parity region is refreshed at the second refresh rate.

公开(公告)号：US09824046B2

公开(公告)日：2017-11-21

申请号：US14337844

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Terrence Brian Remple ,  Devdutt Patnaik ,  Jay Yu Jae Choi ,  Yanru Li

IPC: G06F3/00 ,  G06F13/38 ,  H04L9/08 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4291 ,  G06F2213/0042 ,  G06F2213/3854 ,  H04L9/0838

Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

公开(公告)号：US09734073B2

公开(公告)日：2017-08-15

申请号：US14929083

申请日：2015-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Yanru Li

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0804

CPC classification number: G06F12/0862 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/6026 ,  G06F2212/7203

Abstract: Systems and methods for improved flash memory performance in a portable computing device are presented. In a method, a value N corresponding to an amount of prefetch data to be retrieved from the flash memory is determined. An access request for a flash memory is received at a cache controller in communication with a cache memory. A determination is made whether the access request for the flash memory corresponds to a portion of data stored in the cache memory. If the access request for the flash memory corresponds to the portion of data, the portion of data is returned in response to the access request. Otherwise, an N amount of prefetch data is retrieved from the flash memory and stored in the cache memory. The value N is incremented based on a cache hit percentage for the cache memory.

公开(公告)号：US20160335190A1

公开(公告)日：2016-11-17

申请号：US14710693

申请日：2015-05-13

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Azzedine Touzni

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0888 ,  G06F12/084 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/1045 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/65 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

Abstract translation: 方面包括用于实现系统高速缓存的组件高速缓存的高速缓存维护或状态操作的计算设备，系统和方法。 计算设备可以生成组件高速缓存配置表，将组件高速缓存的至少一个组件高速缓存指示符分配给组件高速缓存的主设备，并且通过集中控制实体将至少一个控制寄存器映射到组件高速缓存指示器。 计算设备可以存储组件高速缓存指示符，使得组件高速缓存指示符可被组件高速缓存的主机访问，用于发现系统高速缓存的虚拟化视图，并且发出用于绕过集中控制实体的组件高速缓存的高速缓存维护或状态命令 。 计算设备可以通过与高速缓存维护或状态命令相关联的控制寄存器以及绕过集中控制实体的组件高速缓存来接收高速缓存维护或状态命令。

公开(公告)号：US09299457B2

公开(公告)日：2016-03-29

申请号：US14187279

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter T. Chun ,  Yanru Li ,  Xiangyu Dong ,  Jungwon Suh ,  Jung Pill Kim ,  Deepti Vijayalakshmi Sriramagiri

IPC: G11C29/00 ,  G11C29/44 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02

CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误的数量超过错误计数阈值，则退出对应于物理地址的内核页面。

公开(公告)号：US20140281283A1

公开(公告)日：2014-09-18

申请号：US13798803

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Assaf Shacham ,  Amit Gil ,  Erez Tsidon ,  Yanru Li ,  Azzedine Touzni

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/462 ,  G06F9/463 ,  G06F9/52 ,  G06F9/544 ,  G06F11/0757 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

Abstract translation: 描述了使用多端口共享非易失性存储器的有效技术，其减少了诸如调制解调器控制处理器之类的专用功能特定处理器的存储器访问中的延迟。 调制解调器处理器抢占正在从多端口共享非易失性存储器闪存器件访问数据的主处理器，允许调制解调器处理器快速访问闪存设备中的数据。 抢占过程使用由寻求访问并中断处理器被抢占的处理器发起的门铃中断。 抢占后，主机处理器可以恢复或重新启动数据访问。 处理器的访问控制利用硬件信号量原子控制机制。 共享的非易失性存储器模块的功率控制包括至少一个不活动定时器，以指示何时可以安全地减少或关闭共享的非易失性存储器模块的电源电压。 共享内存的任何处理器可能会重新启动电源，从而可以快速访问数据。

公开(公告)号：US10579516B2

公开(公告)日：2020-03-03

申请号：US15457899

申请日：2017-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  William Kimberly

IPC: G06F1/3287 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234 ,  G06F1/3221 ,  G06F1/3225 ,  G06F9/50

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

公开(公告)号：US10387333B2

公开(公告)日：2019-08-20

申请号：US15399625

申请日：2017-01-05

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Chun ,  Yanru Li

IPC: G06F21/79 ,  G06F12/14 ,  G06F21/60

Abstract: Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.