公开(公告)号：US09270287B2

公开(公告)日：2016-02-23

申请号：US14490952

申请日：2014-09-19

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhu ,  Xiaohua Kong ,  Nam Van Dang

IPC: H03L7/08 ,  H03L7/099 ,  H04L7/027 ,  H04L7/033

CPC classification number: H03L7/0802 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/0338

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract translation: 门控压控振荡器具有四个相同结构的延迟单元，每个延迟单元通过连接到其他延迟单元的相同数量的输入端而具有相同的输出负载。 可选地，四相采样时钟从延迟单元输出中选择并在四相采样器处采样输入信号。 可选地，边沿检测器将门控压控振荡器的相位同步到NRZ位。 可选地，可变采样率选择来自延迟单元的不同相位以选择以较低速率对NRZ位进行采样。 可选地，脉冲宽度调制（PWM）模式将采样时钟的相位同步到采样PWM符号并恢复编码比特。

公开(公告)号：US09209788B2

公开(公告)日：2015-12-08

申请号：US14228049

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Xiaohua Kong ,  Zhi Zhu ,  Jie Xu

IPC: H03K19/0175 ,  H03K3/356

Abstract: A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage.

公开(公告)号：US09203391B2

公开(公告)日：2015-12-01

申请号：US14258980

申请日：2014-04-22

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhu ,  Xiaohua Kong ,  Li Sun ,  Jie Xu

IPC: H04L7/00 ,  H03K9/08

CPC classification number: H03K9/08 ,  G06F13/4072 ,  H04L25/4902 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient.

Abstract translation: 公开了用于解码脉宽调制（PWM）数据的系统和方法。 示例解码器用单向脉冲滤波器对数据输入信号进行滤波。 单面脉冲滤波器抑制数据输入信号的短脉冲，并通过长脉冲。 示例解码器在数据输入信号的每个位时间结束时锁存经滤波的数据信号。 由单侧脉冲滤波器抑制的脉冲的持续时间可被校准，以补偿电路变化并允许解码器以各种数据速率工作。 解码器可以在小的集成电路区域中实现，并且可以是功率效率的。

公开(公告)号：US20150304134A1

公开(公告)日：2015-10-22

申请号：US14257848

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Madjid Hafizi ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li

IPC: H04L25/02 ,  H04L7/00

CPC classification number: H04L25/0276 ,  H03K5/12 ,  H03K19/018528 ,  H04L7/0091

Abstract: A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers.

Abstract translation: 用于在通信链路上发送串行数据的驱动器电路组合电压模式和电流模式驱动器。 驱动电路使用电压模式驱动器作为主输出驱动器。 一个或多个辅助电流模式驱动器与电压模式驱动器并联连接，以通过向输出中注入电流来调整输出信号。 电压模式驱动器提供大部分输出驱动器。 因此，输出驱动器电路可以提供与电压模式驱动器相关联的功率效率益处。 电流模式驱动器可以提供例如预加重，电平调整，偏斜补偿和输出信号的其它修改。 因此，驱动器电路还可以提供与当前模式驱动器相关联的信号调节能力。

公开(公告)号：US10965442B2

公开(公告)日：2021-03-30

申请号：US16150123

申请日：2018-10-02

Applicant: QUALCOMM Incorporated

Inventor： Eskinder Hailu ,  Bupesh Pandita ,  Jon Boyette ,  Hadi Goudarzi ,  Yong Suk Jun ,  Zhi Zhu ,  Minhan Chen

IPC: H04L7/033 ,  G04F10/00 ,  H04L7/00 ,  H03K3/037 ,  H03K5/159

Abstract: A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

公开(公告)号：US10084621B2

公开(公告)日：2018-09-25

申请号：US15422050

申请日：2017-02-01

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

IPC: H03D3/18 ,  H03D3/24 ,  H04L25/03 ,  H04L12/26 ,  H04L27/00

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：US09722828B2

公开(公告)日：2017-08-01

申请号：US14862677

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Li Sun ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li ,  Dong Ren

IPC: H04L25/00 ,  H04L27/01 ,  H04L25/03 ,  H04L25/02

CPC classification number: H04L27/01 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03006 ,  H04L25/03146 ,  H04L25/03878

Abstract: In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

公开(公告)号：US20170139872A1

公开(公告)日：2017-05-18

申请号：US14939020

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： William Knox Ladd ,  Kevin Wayne Spears ,  Mark Wesley Vilas ,  Zhi Zhu

IPC: G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4027 ,  H03M9/00

Abstract: Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus. In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a high-speed parallel bit stream and then serializes the converted high-speed parallel bit stream based on a high-speed reference frequency. In another aspect, a data receiving circuit recovers the low-speed parallel bit stream from the high-speed parallel bit stream if the low-speed parallel bit stream is determined to exist in the high-speed parallel bit stream. By serializing and deserializing the low-speed parallel bit stream based on the high-speed reference frequency, it is possible to communicate the high-speed parallel bit stream and the low-speed parallel bit stream over the high-speed serial bus without requiring additional serializers and deserializers, thus reducing component costs and implementation complexities in both the transmitting circuit and the receiving circuit.

公开(公告)号：US20170085403A1

公开(公告)日：2017-03-23

申请号：US14862677

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Li Sun ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li ,  Dong Ren

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L27/01 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03006 ,  H04L25/03146 ,  H04L25/03878

Abstract: In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

公开(公告)号：US20160079942A1

公开(公告)日：2016-03-17

申请号：US14486885

申请日：2014-09-15

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Li Sun ,  Zhi Zhu

IPC: H03F3/45 ,  H04B1/16 ,  H04L25/02 ,  H03F3/183

CPC classification number: H03F3/45071 ,  H03F3/183 ,  H03F3/45179 ,  H03F3/45677 ,  H03F3/45713 ,  H03F2200/129 ,  H03F2200/255 ,  H03F2200/36 ,  H03F2200/453 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45112 ,  H03F2203/45302 ,  H03F2203/45306 ,  H03F2203/45418 ,  H03F2203/45422 ,  H03F2203/45424 ,  H04B1/16 ,  H04L25/0272

Abstract: In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage.

Abstract translation: 在一个实施例中，接收机包括具有差分输入和差分输出的差分共栅放大器，其中差分输入包括第一输入和第二输入，并且差分共栅放大器被配置为放大输入差分信号 在差分输入处的差分输出处的放大的差分信号。 接收机还包括被配置为感测输入差分信号的共模电压的共模电压传感器，复制电路被配置为产生在第一和第二和第二至少一个处跟踪直流（DC）电压的复制电压 第二输入和比较器，被配置为将感测的共模电压与复制电压进行比较，并且基于比较来调整输入到差分公共栅放大器的第一偏置电压，其中DC电压取决于第一偏置电压 。