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31.发明申请公开(公告)号：US20190173697A1
公开(公告)日：2019-06-06
申请号：US16182724
申请日：2018-11-07
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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公开(公告)号：US10263761B2
公开(公告)日：2019-04-16
申请号：US16032616
申请日：2018-07-11
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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公开(公告)号：US20190075000A1
公开(公告)日：2019-03-07
申请号：US16057604
申请日：2018-08-07
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.
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公开(公告)号：US10211841B2
公开(公告)日：2019-02-19
申请号：US15667184
申请日：2017-08-02
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC: H03L7/00 , H03K5/156 , G11C7/10 , H03L7/091 , G11C7/22 , H04L7/00 , H04L7/033 , H03L7/08 , H03L7/099 , G11C7/04
Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US20170338979A1
公开(公告)日：2017-11-23
申请号：US15670916
申请日：2017-08-07
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
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Patent Agency Ranking
公开(公告)号：US09768947B2
公开(公告)日：2017-09-19
申请号：US15339342
申请日：2016-10-31
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
CPC classification number: H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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37.发明申请Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 审中-公开具有时钟恢复电路和自适应采样和均衡器时序的接收器公开(公告)号：US20170054576A1
公开(公告)日：2017-02-23
申请号：US15259662
申请日：2016-09-08
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。
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公开(公告)号：US09455825B2
公开(公告)日：2016-09-27
申请号：US14868721
申请日：2015-09-29
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC classification number: H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
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39.发明授权公开(公告)号：US09425997B2
公开(公告)日：2016-08-23
申请号：US14734426
申请日：2015-06-09
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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公开(公告)号：US20150049798A1
公开(公告)日：2015-02-19
申请号：US14363054
申请日：2012-11-30
Applicant: RAMBUS INC.
Inventor： Masum Hossein , Farshid Aryanfar , Jihong Ren , Jared L. Zerbe
CPC classification number: G06F1/3203 , H04B1/12 , H04L7/0054 , H04L7/033 , H04L25/03006 , H04L25/03012 , H04L25/03057 , H04L25/03127 , H04L25/03146 , H04L25/03853 , H04L2025/03433
Abstract: A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI.
Abstract translation: 公开了一种接收机集成电路，其包括滤波器和线性均衡电路。 滤波器具有用于接收主要抽头和前置光标抽头的信号符号的输入，以减少作用在数据符号上的前标ISI。 线性均衡电路耦合到输出并与滤波器配合以进一步减少ISI。
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