公开(公告)号：US20210134818A1

公开(公告)日：2021-05-06

申请号：US16676114

申请日：2019-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L27/11534 ,  H01L27/11526

Abstract: A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.

公开(公告)号：US20210043753A1

公开(公告)日：2021-02-11

申请号：US17080127

申请日：2020-10-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/28

Abstract: A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

公开(公告)号：US20190035800A1

公开(公告)日：2019-01-31

申请号：US16020094

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Atsushi YOSHITOMI

IPC: H01L27/11573 ,  H01L27/11568

CPC classification number: H01L27/11573 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234

Abstract: To provide a semiconductor device capable of having an ONO-film-configuring second oxide film with an optimized thickness. The semiconductor device has a semiconductor substrate having a first surface, a first gate insulating film placed on the first surface located in a first transistor formation region, and a second gate insulating film placed on the first surface located in a second transistor formation region. The first gate insulating film has a first oxide film, a first nitride film placed thereon, and a second oxide film placed thereon. The second oxide film includes a first layer and a second layer placed thereon. The height of the first surface in a region where the second insulating film is placed is lower than that in a region where the first gate insulating film is placed. The nitrogen concentration in the first layer is higher than that in the second layer.

公开(公告)号：US20180182767A1

公开(公告)日：2018-06-28

申请号：US15796815

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L27/1157 ,  H01L23/528 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L23/528 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.

公开(公告)号：US20170330891A1

公开(公告)日：2017-11-16

申请号：US15486741

申请日：2017-04-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L27/11568 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L27/11573 ,  H01L21/324 ,  H01L21/28 ,  H01L29/792 ,  H01L21/265

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28008 ,  H01L21/28282 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor device having a memory cell for a split-gate MONOS memory with a halo region, which prevents miswriting in the memory cell and worsening of short channel characteristics. In the method, a first diffusion layer of a drain region and a second diffusion layer of a source region in the memory cell for the MONOS memory are formed in different ion implantation steps. The steps are carried out so that the first diffusion layer has a smaller formation depth than the second diffusion layer. After the formation of the layers, the impurities inside the first and second diffusion layers are diffused by heat treatment to form a first diffusion region and a second diffusion region.

公开(公告)号：US20160372537A1

公开(公告)日：2016-12-22

申请号：US15256285

申请日：2016-09-02

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02 ,  H01L27/115 ,  H01L27/06

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20160225902A1

公开(公告)日：2016-08-04

申请号：US15093048

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

公开(公告)号：US20160099358A1

公开(公告)日：2016-04-07

申请号：US14872089

申请日：2015-09-30

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Shoji YOSHIDA

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7923 ,  H01L21/28176 ,  H01L21/28282 ,  H01L21/3003 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.

Abstract translation: 包括非易失性存储单元和场效应晶体管在一起的半导体器件性能得到改善。 在制造半导体器件的方法中，在半导体晶片的热处理之前，在其中将具有存储单元的区域中覆盖栅电极和玛瑙绝缘膜的含氢绝缘膜形成含氢绝缘膜， 以及暴露其中将具有配置外围电路的MISFET的区域。 因此，含氢绝缘膜中的氢扩散到栅极绝缘膜和半导体衬底之间的界面，从而选择性地修复界面处的缺陷。

公开(公告)号：US20140302668A1

公开(公告)日：2014-10-09

申请号：US14308667

申请日：2014-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA

IPC: H01L21/02 ,  H01L21/265 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/792 ,  H01L21/02214 ,  H01L21/26513 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.

Abstract translation: 在包括非易失性存储器的半导体器件的性能方面实现了改进。 在分闸门非易失性存储器中，在存储栅电极和p型阱之间以及控制栅电极和存储栅电极之间形成绝缘膜。 在绝缘膜中，存储栅极电极的下表面和半导体衬底的上表面之间的部分具有氧化硅膜和置于氧化硅膜之间的氮化硅膜。 在绝缘膜中，控制栅电极的侧表面与存储栅电极的侧表面之间的部分由氧化硅膜形成，并且不具有氮化硅膜。