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    ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING
    31.
    发明申请
    ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING 有权
    通过使用硬掩模进行偏角平铺图案，在高K金属盖板上增强了盖层的整体性

    公开(公告)号：US20100330757A1

    公开(公告)日：2010-12-30

    申请号：US12821583

    申请日：2010-06-23

    申请人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

    发明人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

    IPC分类号： H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

    摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

    摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。

    MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
    33.
    发明申请
    MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE 有权
    用于减少半导体器件的接触层的介电材料中的失速形成的间隔材料的多步沉积

    公开(公告)号：US20100289083A1

    公开(公告)日：2010-11-18

    申请号：US12776674

    申请日：2010-05-10

    申请人： Markus Lenski ,  Kerstin Ruttloff ,  Volker Jaschke ,  Frank Seliger

    发明人： Markus Lenski ,  Kerstin Ruttloff ,  Volker Jaschke ,  Frank Seliger

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/823468 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823425

    摘要： In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.

    摘要翻译： 在先进的半导体器件中，可以基于多工段沉积技术形成间隔元件，其中可以应用间隔材料的各个子层的一定程度的变化性，例如不同的厚度，以便 在随后的各向异性蚀刻工艺期间增强蚀刻条件。 因此，当使用应力诱导介电材料时，改进形状的间隔元件可能导致优异的沉积条件。 因此，由于紧密封装的设备区域（例如静态RAM区域）中的接触故障导致的屈服损失可能会降低。

    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION
    34.
    发明申请
    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION 有权
    具有嵌入式SI / GE材料的晶体管具有减少偏移到通道区域

    公开(公告)号：US20100078689A1

    公开(公告)日：2010-04-01

    申请号：US12552642

    申请日：2009-09-02

    申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

    摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

    Method of forming sidewall spacers
    36.
    发明授权
    Method of forming sidewall spacers 有权
    形成侧墙的方法

    公开(公告)号：US07316975B2

    公开(公告)日：2008-01-08

    申请号：US11177216

    申请日：2005-07-08

    申请人： Markus Lenski ,  Wolfgang Buchholtz ,  Andy Wei ,  Michael Raab

    发明人： Markus Lenski ,  Wolfgang Buchholtz ,  Andy Wei ,  Michael Raab

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/823468

    摘要： A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

    摘要翻译： 提供了包括第一晶体管元件和第二晶体管元件的衬底。 一层材料沉积在第一晶体管元件和第二晶体管元件上。 材料层的一部分被修饰，其可以例如通过用离子照射部分或执行各向同性蚀刻工艺来实现，以减小其厚度。 执行适于比位于第二晶体管元件上方的层的未修改部分更快地去除材料层的修饰部分的蚀刻工艺。

    Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas
    38.
    发明授权
    Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas 有权
    在漏极和源极区域中包括高k金属栅电极结构和外延形成的半导体材料的互补晶体管

    公开(公告)号：US08835209B2

    公开(公告)日：2014-09-16

    申请号：US13370944

    申请日：2012-02-10

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    IPC分类号： H01L21/00 ,  H01L21/70 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for N-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

    摘要翻译： 当形成包括具有减小的栅极长度的互补晶体管的复杂半导体器件时，可以基于单独提供的半导体合金（例如用于P沟道晶体管的硅/锗合金）和用于磷/磷半导体合金的硅/磷半导体合金 N沟道晶体管。 为此，可以应用优异的硬掩模图案化方案，以提供与复杂的替代栅极方法的兼容性，同时避免不适当的工艺不均匀性，特别是关于去除电介质盖层。

    Superior stability of characteristics of transistors having an early formed high-K metal gate
    39.
    发明授权
    Superior stability of characteristics of transistors having an early formed high-K metal gate 有权
    具有早期形成的高K金属栅极的晶体管的特性的优异的稳定性

    公开(公告)号：US08652917B2

    公开(公告)日：2014-02-18

    申请号：US13478519

    申请日：2012-05-23

    申请人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    发明人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    IPC分类号： H01L21/336

    CPC分类号： H01L21/02057 ,  H01L21/0209 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/51 ,  H01L29/66636 ,  H01L29/7848

    摘要： When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.

    摘要翻译： 当在高k金属栅电极结构和应变诱导半导体合金的基础上形成复杂的晶体管时，在形成空腔之后应用优良的湿式清洗工艺策略，以减少敏感栅极材料的过度修改， k电介质材料，含金属的电极材料等，以及阈值电压调整用半导体合金的变形例。 因此，与常规策略相比，不同宽度的晶体管的阈值电压的显着依赖性可以显着降低。