公开(公告)号：US09306027B2

公开(公告)日：2016-04-05

申请号：US14548527

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Toshiyuki Takewaki ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

Abstract translation: 改善了半导体器件的特性。 半导体器件形成为具有在衬底，阻挡层，在开口区域中穿过阻挡层的沟槽并且到达沟道层的某一点的沟槽层，布置在沟槽中的栅极电极 栅极绝缘膜，以及形成在开口区域外侧的阻挡层上的绝缘膜。 然后，绝缘膜具有富Si硅氮化膜和位于其下方的富氮氮化硅膜的叠层结构。 因此，绝缘膜的上层被设定为富Si硅氮化膜。 这使得能够提高击穿电压，并且还能够提高耐蚀刻性。 而绝缘膜的下层被设定为富N的氮化硅膜。 这可以抑制崩溃。

公开(公告)号：US09269803B2

公开(公告)日：2016-02-23

申请号：US13937846

申请日：2013-07-09

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Takashi Inoue ,  Tatsuo Nakayama ,  Ryohei Nega ,  Masaaki Kanazawa ,  Hironobu Miyamoto

IPC: H01L29/78 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/778 ,  H01L29/51 ,  H01L29/20

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

Abstract translation: 提高了由氮化物半导体材料制成的场效应晶体管的可靠性。 欧姆电极包括被隔离以彼此分离的多个单元电极。 由此，能够防止在y轴方向（负方向）在单位电极中流通导通电流。 此外，在各单元电极中，可以防止沿y轴方向（负方向）流动的通态电流的电流密度增加。 结果，可以提高欧姆电极的电迁移电阻。

公开(公告)号：US20150041821A1

公开(公告)日：2015-02-12

申请号：US14330995

申请日：2014-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Masaaki Kanazawa ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Hironobu Miyamoto ,  Ryohei Nega

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1−x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0

Abstract translation: 电极与AlGaN层欧姆接触。 半导体器件SD具有氮化物半导体层GN2和Al x Ga（1-x）N层AGN（以下称为“AlGaN层AGN”）和Al电极DE，SE。 在AlGaN层AGN中，满足0

公开(公告)号：US11489047B2

公开(公告)日：2022-11-01

申请号：US17068378

申请日：2020-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Okamoto ,  Nobuo Machida

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06

Abstract: To improve an on-resistance of a semiconductor device. A plurality of collector regions are formed at a predetermined interval on a bottom surface of a drift layer made of SiC. Next, on the bottom surface of the drift layer, both of the drift layer and a collector region via a silicide layer are connected to a collector electrode.

公开(公告)号：US11276784B2

公开(公告)日：2022-03-15

申请号：US17121143

申请日：2020-12-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Okamoto ,  Nobuo Machida ,  Kenichi Hisada

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US10249727B2

公开(公告)日：2019-04-02

申请号：US15670982

申请日：2017-08-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Okamoto

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417

Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.

公开(公告)号：US10014403B2

公开(公告)日：2018-07-03

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/15 ,  H01L29/201 ,  H01L21/027 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US20180151377A1

公开(公告)日：2018-05-31

申请号：US15882687

申请日：2018-01-29

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

公开(公告)号：US09831339B2

公开(公告)日：2017-11-28

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Ichiro Masumoto ,  Yasuhiro Okamoto ,  Shinichi Miyake ,  Hiroshi Kawaguchi

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US09761682B2

公开(公告)日：2017-09-12

申请号：US14961545

申请日：2015-12-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Okamoto

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/42368 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/66462 ,  H01L29/7786

Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.