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公开(公告)号：US07610447B2
公开(公告)日：2009-10-27
申请号：US09797099
申请日：2001-02-28
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the system is fully populated, there is a one-to-one correspondence between signal line sets and memory modules. In systems that are not fully populated, the system is configurable to use a plurality of the signal line sets for a single memory module.
摘要翻译： 这里描述的是具有与多个连接器或模块位置中的每一个相关联的点对点信号线集合的点对点存储器通信架构。 当系统完全填充时，信号线组和存储器模块之间存在一一对应关系。 在未完全填充的系统中，系统可配置为对于单个存储器模块使用多个信号线组。
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公开(公告)号：US07369444B2
公开(公告)日：2008-05-06
申请号：US11434695
申请日：2006-05-16
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
摘要翻译： 根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。
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公开(公告)号：US07209397B2
公开(公告)日：2007-04-24
申请号：US11094137
申请日：2005-03-31
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.
摘要翻译： 一种具有时钟倍增器电路的存储器件。 存储器件包括时钟发生电路，用于接收具有第一频率的第一时钟信号并产生具有第二频率的第二频率的第二频率，该第二频率是第一频率的倍数。 存储器件包括用于以第二时钟信号的频率接收数据的数据接收电路，并且还可以包括以第二时钟信号的频率发送数据的数据发送电路。 此外，时钟发生电路还可以产生具有也是第一频率的倍数的第三频率的第三时钟信号，第三时钟信号被提供给存储器件的控制电路，以便接收控制和/或 地址信号。 在特定实施例中，第二频率是第一频率的四倍或八倍，第三频率是第一频率的两倍。
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公开(公告)号：US07187572B2
公开(公告)日：2007-03-06
申请号：US10353405
申请日：2003-01-29
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
摘要翻译： 根据实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。
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35.发明授权公开(公告)号：US08924680B2
公开(公告)日：2014-12-30
申请号：US12745494
申请日：2008-04-11
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译： 存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。 请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。 所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。 每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。
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公开(公告)号：US08320202B2
公开(公告)日：2012-11-27
申请号：US11767983
申请日：2007-06-25
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译： 一种具有第一和第二存储器件和终端部件的存储器系统。 第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线， 到第二存储设备。 控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。 提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。
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公开(公告)号：US08144792B2
公开(公告)日：2012-03-27
申请号：US11754102
申请日：2007-05-25
IPC分类号： H04B3/00
CPC分类号： H04L1/242 , G11C7/04 , G11C7/1057 , G11C7/1084 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/2254 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12 , H04L27/00
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
摘要翻译： 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。
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38.发明申请公开(公告)号：US20110219197A1
公开(公告)日：2011-09-08
申请号：US12745494
申请日：2008-04-11
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译： 存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。 请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。 所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。 每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。
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公开(公告)号：US20100061047A1
公开(公告)日：2010-03-11
申请号：US12538613
申请日：2009-08-10
IPC分类号： G06F1/16
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译： 描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。 一个拓扑结构可编程，以支持轨到轨或半电源终端。 另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。 终端电压和阻抗也可能会被调整。
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40.发明申请公开(公告)号：US20090248972A1
公开(公告)日：2009-10-01
申请号：US12482626
申请日：2009-06-11
IPC分类号： G06F12/10
CPC分类号： G11C11/406 , G06F12/00 , G06F13/1605 , G11C11/40603
摘要： Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.
摘要翻译： 描述了执行重叠刷新和数据访问（读或写）事务的动态存储器系统，其最小化刷新事务对存储器性能的影响。 存储器系统支持针对不同银行的独立且同时的激活和预充电操作。 两组地址寄存器使系统能够同时指定用于刷新和数据访问事务的不同库。
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