公开(公告)号：US20050073880A1

公开(公告)日：2005-04-07

申请号：US10680464

申请日：2003-10-07

申请人： Kenneth Smith ,  Frederick Perner

发明人： Kenneth Smith ,  Frederick Perner

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： H01L27/222 ,  G11C11/16

摘要： The present invention provides a magnetic memory. In one embodiment, the magnetic memory includes a first line having a first cross-sectional area. A second line is provided having a second cross-sectional area different from the first cross-sectional area. A magnetic memory cell stack is positioned between the first line and the second line.

摘要翻译： 本发明提供一种磁存储器。 在一个实施例中，磁存储器包括具有第一横截面积的第一线。 提供具有不同于第一横截面积的第二横截面积的第二线。 磁存储单元堆叠位于第一线和第二线之间。

公开(公告)号：US20050007823A1

公开(公告)日：2005-01-13

申请号：US10614581

申请日：2003-07-07

申请人： Kenneth Smith ,  Corbin Champion ,  Stewart Wyatt ,  Frederick Perner

发明人： Kenneth Smith ,  Corbin Champion ,  Stewart Wyatt ,  Frederick Perner

IPC分类号： G11C11/15 ,  G11C16/04

CPC分类号： G11C11/15

摘要： A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.

摘要翻译： 一种包括存储单元串的数据存储装置。 存储单元串包括第一存储单元和第二存储单元。 该装置还包括耦合到第一存储单元和第二存储单元之间的节点的电路。 电路被配置为响应于提供给存储器单元串并且第一存储器单元被写入第一状态的电压来检测节点处的电压变化。

公开(公告)号：US06781906B2

公开(公告)日：2004-08-24

申请号：US10299501

申请日：2002-11-19

申请人： Frederick Perner ,  Lung Tran

发明人： Frederick Perner ,  Lung Tran

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/16 ,  G11C2207/063 ,  G11C2207/2254

摘要： A memory cell sensor including an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.

摘要翻译： 一种存储单元传感器，包括用于感测存储单元的逻辑状态的积分器。 积分器校准电路为积分器提供校正偏置，校正偏置基于初始积分器输出值和参考值之间的差异。 另一个实施例包括一种感测存储器单元的逻辑状态的方法。 存储器单元被积分器感测。 该方法包括当积分器的校正偏置为零时确定初始积分器输出值，通过将初始积分器输出值与参考值进行比较产生校正值，并将校正值应用于积分器的校正偏置。

公开(公告)号：US08933431B2

公开(公告)日：2015-01-13

申请号：US14006719

申请日：2011-03-29

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： H01L29/06 ,  H01L47/00 ,  G11C5/06 ,  H01L25/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/12 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.

摘要翻译： 存储器阵列具有多个导体结构。 每个导体结构具有沿第一方向延伸的顶部线段，沿着与第一方向成一定角度的第二方向延伸的中间线段，沿与第一方向相反的方向延伸的底部线段，以及连接 顶部，中间和底部线段。 存储器阵列的上平面中的多个存储单元形成在每个导体结构的中间线段与相邻导体结构的顶部线段的交点处，并且下部平面中的多个存储单元形成在相交处 每个导体结构的中间线段与相邻导体结构的底部线段。

公开(公告)号：US08570785B2

公开(公告)日：2013-10-29

申请号：US12788161

申请日：2010-05-26

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C5/063 ,  G11C13/0002 ,  G11C2013/0045 ,  G11C2211/5645

摘要： A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.

摘要翻译： 用于读取交叉开关阵列中的存储器元件的方法包括切换连接到交叉开关阵列的目标存储器元件的列线以连接到电流镜的输入; 将误差电压施加到交叉开关阵列的未选择的行; 对连接到目标存储元件的行线施加感测电压; 并测量电流镜的输出电流。

公开(公告)号：US20130223132A1

公开(公告)日：2013-08-29

申请号：US13883510

申请日：2011-02-28

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C13/0007 ,  G11C27/02 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057

摘要： A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.

摘要翻译： 用于感测交叉点阵列中的电阻式开关装置的电阻状态的读取电路具有连接到阵列中的电阻式开关装置的选定列线的等电位前置放大器，以传送读取电流，同时将选定的列线保持在参考电压 靠近施加到阵列的未选择行线的偏置电压。 读取电路包括用于产生等电位前置放大器的参考电压的参考电压产生部件。 参考电压产生组件通过所选列线对偏置电压进行采样，并将一个小增量加到采样的偏置电压上，以形成参考电压。

公开(公告)号：US08472262B2

公开(公告)日：2013-06-25

申请号：US12813003

申请日：2010-06-10

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： G11C7/10

CPC分类号： G11C7/065 ,  G11C5/063 ,  G11C7/067 ,  G11C13/0007 ,  G11C13/004 ,  G11C2207/063

摘要： A sense amplifier for reading the data stored in a crossbar array includes a storage transistor to store a first voltage resulting from an electric current from a column line connected to a target memory element while the target memory element is half-selected, the first voltage resulting from bias voltages applied to row lines not connected to the target memory element; a mirror transistor to store a second voltage resulting from an electric current from the column line while the target memory element is fully selected; a cross-coupled inverter circuit having a first branch connected to the storage transistor and a second branch connected to the mirror transistor; and an output node to output a signal from the first branch of the cross-coupled inverter circuit, the signal based on a comparison between the first voltage stored in the storage transistor and the second voltage across the mirror transistor.

摘要翻译： 用于读取存储在交叉开关阵列中的数据的读出放大器包括一个存储晶体管，用于在目标存储器元件被半选择时存储来自连接到目标存储元件的列线的电流产生的第一电压，产生第一电压 从施加到未连接到目标存储元件的行线的偏置电压; 反射镜晶体管，用于在目标存储元件完全选择时存储来自列线的电流产生的第二电压; 交叉耦合的反相器电路，具有连接到存储晶体管的第一分支和连接到反射镜晶体管的第二分支; 以及输出节点，用于输出来自交叉耦合的反相器电路的第一分支的信号，该信号基于存储在存储晶体管中的第一电压与镜面晶体管两端的第二电压之间的比较。

公开(公告)号：US08451666B2

公开(公告)日：2013-05-28

申请号：US12787857

申请日：2010-05-26

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C7/062 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2213/77

摘要： A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying bias voltages to row lines of the crossbar array; storing an output voltage of the source follower in a storage element; applying a sense voltage to a row line connected to the target memory element; and outputting a difference between the voltage stored in the storage element and an output voltage of the source follower while the sense voltage is applied to the row line.

摘要翻译： 一种用于读取交叉开关阵列内的存储元件的方法，所述方法包括通过向源极跟随器施加电源电压来选择连接到所述交叉开关阵列的目标存储器元件的列线，所述源极跟随器的栅极端子连接到所述列 线; 向所述交叉开关阵列的行线施加偏置电压; 将源极跟随器的输出电压存储在存储元件中; 对连接到目标存储元件的行线施加感测电压; 并且当所述感测电压被施加到所述行线时，输出存储在所述存储元件中的电压与所述源极跟随器的输出电压之间的差。

公开(公告)号：US20110292713A1

公开(公告)日：2011-12-01

申请号：US12788161

申请日：2010-05-26

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/004 ,  G11C5/063 ,  G11C13/0002 ,  G11C2013/0045 ,  G11C2211/5645

摘要： A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.

摘要翻译： 用于读取交叉开关阵列中的存储器元件的方法包括切换连接到交叉开关阵列的目标存储器元件的列线以连接到电流镜的输入; 将误差电压施加到交叉开关阵列的未选择的行; 对连接到目标存储元件的行线施加感测电压; 并测量电流镜的输出电流。

公开(公告)号：US20070096815A1

公开(公告)日：2007-05-03

申请号：US11266861

申请日：2005-11-03

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： H03F3/45

CPC分类号： H03F3/45179 ,  G11C7/04 ,  G11C7/062 ,  G11C7/08 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H03F1/52 ,  H03F3/45744 ,  H03F2203/45048 ,  H03F2203/45342 ,  H03F2203/45366

摘要： A combined analog and digital calibration circuit and method for adjusting an output offset voltage of a differential amplifier circuit are provided. The circuit comprises a digitally controlled voltage divider positioned between at least one isolated well and a controllable voltage source, a controllable voltage source controlled by an initial constant current and a variable current, and a controller to modify the variable current to continuously adjust the back gate control voltage. The method comprises adjusting a control voltage of at least one of a pair of input transistors using a back gate control voltage, providing an analog current to establish a back gate control voltage, and altering the analog current when the back gate control voltage causes an output offset voltage to differ from a reference voltage by more than a predetermined quantity.

摘要翻译： 提供了用于调整差分放大器电路的输出偏移电压的组合的模拟和数字校准电路和方法。 该电路包括位于至少一个隔离阱和可控电压源之间的数字控制分压器，由初始恒定电流和可变电流控制的可控电压源，以及控制器，用于修改可变电流以连续调节后门 控制电压。 该方法包括使用背栅控制电压来调节一对输入晶体管中的至少一个的控制电压，提供模拟电流以建立背栅控制电压，以及当背栅控制电压导致输出时改变模拟电流 偏移电压与参考电压不同的预定量。