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349 条记录 (耗时 0.031 秒)

    Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
    31.
    发明授权
    Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same 有权

    公开(公告)号：US07276411B2

    公开(公告)日：2007-10-02

    申请号：US11137001

    申请日：2005-05-25

    申请人： Richard K. Williams ,  Wayne B. Grabowski

    发明人： Richard K. Williams ,  Wayne B. Grabowski

    IPC分类号： H01L21/8242 ,  H01L21/76

    CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

    摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

    Damped disc drive assembly, and method for damping disc drive assembly
    33.
    发明授权
    Damped disc drive assembly, and method for damping disc drive assembly 失效
    阻尼盘驱动组件及阻尼盘驱动组件的方法

    公开(公告)号：US07199970B2

    公开(公告)日：2007-04-03

    申请号：US10698937

    申请日：2003-11-03

    申请人： Daniel E. Boss ,  Richard K. Williams

    发明人： Daniel E. Boss ,  Richard K. Williams

    IPC分类号： G11B33/14

    CPC分类号： G11B25/043 ,  G11B33/08 ,  Y10T29/49025

    摘要： A disc drive assembly is provided including a head disc assembly, a housing having a base and a cover cooperating with one another to form a chamber in which the head disc assembly is housed, and a damper structure in operative association with the housing for dampening noise and/or vibration emanated from the head disc assembly. The damper structure includes a viscoelastic damper layer and a continuous, polymeric constraining layer intimately contacting and encasing the viscoelastic damper layer. The constraining layer has a greater stiffness and higher modulus of dynamic shearing elasticity than the viscoelastic damper layer, and is molded from a high density filler and a moldable compound that is immiscible with the viscoelastic damper layer to provide a discrete interface between the constraining layer and the viscoelastic damper layer.

    摘要翻译： 提供了一种盘驱动器组件，其包括头盘组件，具有基座和与彼此配合的盖的壳体，以形成其中容纳头盘组件的腔室，以及与壳体可操作地相关联的阻尼器结构，用于抑制噪音 和/或从头盘组件发出的振动。 阻尼器结构包括粘弹性阻尼层和紧密接触和包裹粘弹性阻尼层的连续聚合约束层。 约束层具有比粘弹性阻尼层更大的刚性和更高的动态剪切弹性模量，并且由高密度填料和可模制化合物模制而成，其与粘弹性阻尼层不混溶，以在约束层和 粘弹阻尼层。

    Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance
    35.
    发明授权
    Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance 有权
    具有降低的导通电阻的超自对准沟槽门控DMOS的制造工艺

    公开(公告)号：US06756274B2

    公开(公告)日：2004-06-29

    申请号：US10146568

    申请日：2002-05-14

    申请人： Richard K. Williams ,  Wayne Grabowski

    发明人： Richard K. Williams ,  Wayne Grabowski

    IPC分类号： H01L21336

    CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7811

    摘要： A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

    摘要翻译： 超自对准（SSA）结构和制造工艺使用单个光掩模层来定义沟槽门垂直功率DMOSFET的关键特征和尺寸。 单个关键掩模确定沟槽表面尺寸，沟槽之间的硅源体台面宽度以及硅台面接触的尺寸和位置。 接触件与沟槽自对准，消除了在传统沟槽DMOS器件中接触沟槽掩模对准所造成的限制，以避免工艺引起的栅极至源极短路。 硅表面上方的氧化物台阶高度也减少，避免了金属台阶覆盖问题。 多门总线步高也减少了。 所描述的其它特征包括多晶硅二极管形成，控制漏极体二极管击穿的位置，减少栅 - 漏重叠电容，以及利用低热预算处理技术。

    Super-self-aligned trench-gated DMOS with reduced on-resistance
    36.
    发明授权
    Super-self-aligned trench-gated DMOS with reduced on-resistance 有权
    超自对准沟槽门控DMOS，导通电阻降低

    公开(公告)号：US06750507B2

    公开(公告)日：2004-06-15

    申请号：US10146668

    申请日：2002-05-14

    申请人： Richard K. Williams ,  Wayne Grabowski

    发明人： Richard K. Williams ,  Wayne Grabowski

    IPC分类号： H01L218222

    CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7811

    摘要： A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

    摘要翻译： 超自对准（SSA）结构和制造工艺使用单个光掩模层来定义沟槽门垂直功率DMOSFET的关键特征和尺寸。 单个关键掩模确定沟槽表面尺寸，沟槽之间的硅源体台面宽度以及硅台面接触的尺寸和位置。 接触件与沟槽自对准，消除了在传统沟槽DMOS器件中接触沟槽掩模对准所造成的限制，以避免工艺引起的栅极至源极短路。 硅表面上方的氧化物台阶高度也减少，避免了金属台阶覆盖问题。 多门总线步高也减少了。 所描述的其它特征包括多晶硅二极管形成，控制漏极体二极管击穿的位置，减少栅 - 漏重叠电容，以及利用低热预算处理技术。