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31.发明授权Circuitized substrates utilizing smooth-sided conductive layers as part thereof 失效使用平滑侧导电层作为其一部分的电路化基板公开(公告)号：US07838776B2
公开(公告)日：2010-11-23
申请号：US12148271
申请日：2008-04-17
IPC分类号： H05K1/03
CPC分类号： H01L21/4857 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01021 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K3/383 , H05K3/4641 , H05K2201/0355 , H05K2201/09318 , H05K2203/0353 , Y10S428/901 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T428/12556 , Y10T428/12993 , H01L2224/0401
摘要： A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.
摘要翻译： 其中两个导电层（例如，电镀铜箔）被结合（例如层压）到电介质层的电路化衬底。 物理地结合到电介质的两个箔表面中的每一个是光滑的（例如，优选通过化学处理），并且在其上包括薄的有机层，而两个箔的外表面也是光滑的（例如，优选也使用化学处理 步）。 这些导电层中的一个可以用作接地或电压平面，而另一个可以用作具有多个单独信号线作为其一部分的信号平面。 还提供了使用这种电路化基板的电气组件和信息处理系统。
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公开(公告)号：US06264851B1
公开(公告)日：2001-07-24
申请号：US09042876
申请日：1998-03-17
IPC分类号： C23F100
摘要： The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.
摘要翻译： 本发明涉及一种方法，其中印刷电路板可以在中间种子层上使用温和的蚀刻条件以最小数量的制造步骤在无电镀方法中制造，以产生低缺陷的细导线印刷电路板。
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33.发明申请Circuitized substrates utilizing smooth-sided conductive layers as part thereof 失效使用平滑侧导电层作为其一部分的电路化基板公开(公告)号：US20080259581A1
公开(公告)日：2008-10-23
申请号：US12148271
申请日：2008-04-17
CPC分类号： H01L21/4857 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01021 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K3/383 , H05K3/4641 , H05K2201/0355 , H05K2201/09318 , H05K2203/0353 , Y10S428/901 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T428/12556 , Y10T428/12993 , H01L2224/0401
摘要： A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.
摘要翻译： 其中两个导电层（例如，电镀铜箔）被结合（例如层压）到电介质层的电路化衬底。 物理地结合到电介质的两个箔表面中的每一个是光滑的（例如，优选通过化学处理），并且在其上包括薄的有机层，而两个箔的外表面也是光滑的（例如，优选也使用化学处理 步）。 这些导电层中的一个可以用作接地或电压平面，而另一个可以用作具有多个单独信号线作为其一部分的信号平面。 还提供了使用这种电路化基板的电气组件和信息处理系统。
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公开(公告)号：US06388204B1
公开(公告)日：2002-05-14
申请号：US09651010
申请日：2000-08-29
申请人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
IPC分类号： H01R909
CPC分类号： H05K3/462 , H01R4/26 , H05K3/0023 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0307 , Y10S428/901 , Y10T156/1089 , Y10T428/24917
摘要： A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.
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公开(公告)号：US06740819B2
公开(公告)日：2004-05-25
申请号：US10421272
申请日：2003-04-23
申请人： Anilkumar C. Bhatt , Ashwinkumar C. Bhatt , Subahu D. Desai , John M. Lauffer , Voya R. Markovich , Thomas R. Miller
发明人： Anilkumar C. Bhatt , Ashwinkumar C. Bhatt , Subahu D. Desai , John M. Lauffer , Voya R. Markovich , Thomas R. Miller
IPC分类号： H05K706
CPC分类号： H05K3/445 , H05K1/056 , H05K3/0023 , H05K3/0082 , H05K3/4641 , H05K2203/143
摘要： Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.
摘要翻译： 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。
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公开(公告)号：US06608757B1
公开(公告)日：2003-08-19
申请号：US10101277
申请日：2002-03-18
申请人： Anilkumar C. Bhatt , Ashwinkumar C. Bhatt , Subahu D. Desai , John M. Lauffer , Voya R. Markovich , Thomas R. Miller
发明人： Anilkumar C. Bhatt , Ashwinkumar C. Bhatt , Subahu D. Desai , John M. Lauffer , Voya R. Markovich , Thomas R. Miller
IPC分类号： H05K716
CPC分类号： H05K3/445 , H05K1/056 , H05K3/0023 , H05K3/0082 , H05K3/4641 , H05K2203/143
摘要： Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.
摘要翻译： 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。
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公开(公告)号：US06593534B2
公开(公告)日：2003-07-15
申请号：US09812261
申请日：2001-03-19
申请人： Gerald W. Jones , John M. Lauffer , Voya R. Markovich , Thomas R. Miller , James P. Paoletti , Konstantinos I. Papathomas , James R. Stack
发明人： Gerald W. Jones , John M. Lauffer , Voya R. Markovich , Thomas R. Miller , James P. Paoletti , Konstantinos I. Papathomas , James R. Stack
IPC分类号： H01R909
CPC分类号： H05K3/462 , H05K1/115 , H05K3/4069 , H05K2201/0347 , H05K2201/0352 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2203/0554
摘要： A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.
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公开(公告)号：US07615477B2
公开(公告)日：2009-11-10
申请号：US11566956
申请日：2006-12-05
IPC分类号： H01L31/058 , H01L23/495 , H01L23/48 , H01L21/44
CPC分类号： H05K1/0271 , H01L23/49866 , H01L2924/0002 , H05K1/111 , H05K3/384 , H05K3/4092 , H05K2201/0133 , H05K2201/0355 , H05K2203/0307 , H05K2203/1152 , H01L2924/00
摘要： Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.
摘要翻译： 提供了具有降低的BGA焊盘与层压体表面的粘附性的球栅阵列封装及其制造方法。
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公开(公告)号：US07148566B2
公开(公告)日：2006-12-12
申请号：US09817843
申请日：2001-03-26
IPC分类号： H01L21/44
CPC分类号： H05K1/0271 , H01L23/49866 , H01L2924/0002 , H05K1/111 , H05K3/384 , H05K3/4092 , H05K2201/0133 , H05K2201/0355 , H05K2203/0307 , H05K2203/1152 , H01L2924/00
摘要： Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.
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40.发明授权公开(公告)号：US06479093B2
公开(公告)日：2002-11-12
申请号：US10062100
申请日：2002-01-31
申请人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
IPC分类号： B05D512
CPC分类号： H05K3/462 , H01R4/26 , H05K3/0023 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0307 , Y10S428/901 , Y10T156/1089 , Y10T428/24917
摘要： A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.
摘要翻译： 提供了一种层叠电路结构组件，其包括至少两个模块化电路化的平面子组件; 位于每个子组件之间的接合层，并且其中所述子组件和接合层与来自可结合的可固化电介质的固化电介质结合在一起。 子组件和接合层与可结合的导电材料电互连。 接合层包括围绕内部导电层设置的电介质层。 导电层具有通孔，并且介电层各自具有比导电层中的通孔更小的直径的通孔，并且与导电层中的通孔对准。 通孔填充有电可焊接的导电材料，用于在子组件之间提供电接触。
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