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公开(公告)号：US20250078947A1
公开(公告)日：2025-03-06
申请号：US18949589
申请日：2024-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US12205661B2
公开(公告)日：2025-01-21
申请号：US18093560
申请日：2023-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US11551776B2
公开(公告)日：2023-01-10
申请号：US17392382
申请日：2021-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US11031957B2
公开(公告)日：2021-06-08
申请号：US15956960
申请日：2018-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun Jang , Dong-Min Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Se Jin Lim
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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公开(公告)号：US10916314B2
公开(公告)日：2021-02-09
申请号：US16744763
申请日：2020-01-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
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Patent Agency Ranking
公开(公告)号：US10686471B2
公开(公告)日：2020-06-16
申请号：US15821480
申请日：2017-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yaron Shany , Jun Jin Kong
Abstract: A method for repairing a single erasure in a Reed Solomon code in a system of a plurality of n storage nodes and a controller, wherein a content of each storage node is a codeword and each node stores a vector v. The method includes identifying a failed storage node; transmitting an index of the failed storage node to each surviving storage node; multiplying the content of each node i by a j-th component of a vector that is a permutation of elements of vector v that correspond to the surviving storage nodes; determining a trace map of the result and converting the result from an m×r bit representation into a reduced representation of r bits; reconstructing the content of the failed storage node from the reduced representation of each surviving node's content; and outputting the reconstructed content of the failed storage node.
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公开(公告)号：US10389385B2
公开(公告)日：2019-08-20
申请号：US15409724
申请日：2017-01-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yaron Shany , Jun Jin Kong
Abstract: An application specific integrated circuit (ASIC) tangibly encodes a method for fast polynomial updates in fast Chase decoding of binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The method includes the steps of using outputs of a syndrome-based hard-decision (HD) algorithm to find a Groebner basis for a solution module of a modified key equation, upon failure of HD decoding of a BCH codeword received by the ASIC from a communication channel; evaluating polynomials obtained from said Groebner basis at inverses of specified weak-bit locations; and transforming a Groebner basis for a set of flipped weak-bit locations (α1, . . . , αr−1) to a Groebner basis for (α1, . . . , αr), wherein αr is a next weak-bit location, wherein r is a difference between a number of errors and a HD correction radius of the BCH codeword.
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公开(公告)号：US10372534B2
公开(公告)日：2019-08-06
申请号：US15270292
申请日：2016-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Amit Berman , Uri Beitler , Jun Jin Kong
Abstract: A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.
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公开(公告)号：US10164663B2
公开(公告)日：2018-12-25
申请号：US15613659
申请日：2017-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Min Shin , Beom Kyu Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Yeong Geol Song , Se Jin Lim
Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
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公开(公告)号：US20180205398A1
公开(公告)日：2018-07-19
申请号：US15409724
申请日：2017-01-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YARON SHANY , Jun Jin Kong
CPC classification number: H03M13/1545 , H03M13/152 , H03M13/153 , H03M13/453 , H03M13/6502
Abstract: An application specific integrated circuit (ASIC) tangibly encodes a method for fast polynomial updates in fast Chase decoding of binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The method includes the steps of using outputs of a syndrome-based hard-decision (HD) algorithm to find a Groebner basis for a solution module of a modified key equation, upon failure of HD decoding of a BCH codeword received by the ASIC from a communication channel; evaluating polynomials obtained from said Groebner basis at inverses of specified weak-bit locations; and transforming a Groebner basis for a set of flipped weak-bit locations (α1, . . . , αr−1) to a Groebner basis for (α1, . . . , αr), wherein αr is a next weak-bit location, wherein r is a difference between a number of errors and a HD correction radius of the BCH codeword.
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