公开(公告)号：US20190035480A1

公开(公告)日：2019-01-31

申请号：US15699513

申请日：2017-09-08

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Anubhav Khandelwal ,  Changyuan Chen ,  Cynthia Hsu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

公开(公告)号：US10115737B2

公开(公告)日：2018-10-30

申请号：US15893157

申请日：2018-02-09

Applicant: SanDisk Technologies LLC

Inventor： Hoon Cho ,  Jun Wan ,  Ching-Huang Lu

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L29/40 ,  H01L27/11556 ,  H01L21/28

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

公开(公告)号：US20180308556A1

公开(公告)日：2018-10-25

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3459

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

公开(公告)号：US20170345705A1

公开(公告)日：2017-11-30

申请号：US15163236

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Yingda Dong ,  Jayavel Pachamuthu ,  Ching-Huang Lu

IPC: H01L21/768 ,  H01L27/1157 ,  H01L23/528 ,  H01L21/28 ,  H01L23/522 ,  H01L27/11582 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.

公开(公告)号：US20170345470A1

公开(公告)日：2017-11-30

申请号：US15163171

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C7/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/04 ,  G11C7/062 ,  G11C7/22 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

公开(公告)号：US09830963B1

公开(公告)日：2017-11-28

申请号：US15163171

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C7/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/04 ,  G11C7/062 ,  G11C7/22 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

公开(公告)号：US20210202022A1

公开(公告)日：2021-07-01

申请号：US16728716

申请日：2019-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Henry Chin ,  Ching-Huang Lu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.

公开(公告)号：US10685979B1

公开(公告)日：2020-06-16

申请号：US16267625

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L29/792 ,  H01L21/4763 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.

公开(公告)号：US20200005878A1

公开(公告)日：2020-01-02

申请号：US16022373

申请日：2018-06-28

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Han-Ping Chen ,  Chung-Yao Pai ,  Yingda Dong

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.

公开(公告)号：US10482981B2

公开(公告)日：2019-11-19

申请号：US15900093

申请日：2018-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C16/08 ,  G11C11/56 ,  G11C16/24 ,  G11C16/10

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.