公开(公告)号：US11342029B2

公开(公告)日：2022-05-24

申请号：US17034086

申请日：2020-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ken Oowada ,  Huai-Yuan Tseng

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30

Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.

公开(公告)号：US11342006B2

公开(公告)日：2022-05-24

申请号：US16666077

申请日：2019-10-28

Applicant: SanDisk Technologies LLC

Inventor： Kiyohiko Sakakibara ,  Ken Oowada

IPC: G11C5/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L27/11582 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  G11C16/26 ,  H01L21/8234

Abstract: Methods for reducing manufacturing cost and improving the reliability of non-volatile memories using NAND strings with polysilicon channels and p-type doped source lines are described. A NAND string may include a polysilicon channel that is orthogonal to a substrate and connects to a boron doped source line at a source-side end of the NAND string. To reduce the likelihood of the polysilicon channel being cut-off or pinched near the source-side end of the NAND string, a thicker polysilicon channel may be formed near the source-side end of the NAND string while a thinner polysilicon channel may be formed for the remainder of the NAND string by diffusing boron into a first portion of the polysilicon channel corresponding with the thicker polysilicon channel and then etching the polysilicon channel with etchants that exhibit a reduction in their etch rate at a boron concentration above a threshold concentration.

公开(公告)号：US20210174881A1

公开(公告)日：2021-06-10

申请号：US17173023

申请日：2021-02-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US20210173734A1

公开(公告)日：2021-06-10

申请号：US16708383

申请日：2019-12-09

Applicant: SanDisk Technologies LLC

Inventor： Shih-Chung Lee ,  Takashi Murai ,  Ken Oowada

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/30 ,  G06F12/02 ,  G06F13/16 ,  G11C29/12 ,  G11C16/34

Abstract: For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test of a block can be fail stop for critical category errors, but, for recoverable categories, the test continues and tracks the test results to determine a recoverability category for the block and write this onto the die as a bad block flag for each block. These recoverability categories can be incorporated into wear leveling operations.

公开(公告)号：US10978152B1

公开(公告)日：2021-04-13

申请号：US16682730

申请日：2019-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34

Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.

公开(公告)号：US12046302B2

公开(公告)日：2024-07-23

申请号：US17557492

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/3454 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3409

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

公开(公告)号：US11901007B2

公开(公告)日：2024-02-13

申请号：US17507119

申请日：2021-10-21

Applicant: SanDisk Technologies LLC

Inventor： Ken Oowada ,  Natsu Honda

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/0483 ,  G11C16/14 ,  G11C16/3445 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/10 ,  H10B43/27

Abstract: Technology for applying a positive temperature coefficient (Tco) voltage to a control terminal of a dummy select transistor. The dummy select transistor resides on a NAND string having non-volatile memory cells and a regular select transistor. The dummy select transistor is typically ON (or conductive) during memory operations such as selected string program, read, and verify. In an aspect, the positive Tco voltage is applied to the control terminal of a dummy select transistor during a program operation. Applying the positive Tco voltage during program operations reduces or eliminates program disturb to the dummy select transistor. In some aspects, the dummy select transistor is used to generate a gate induced drain leakage (GIDL) current during an erase operation. In some aspects, the dummy select transistor is a depletion mode transistor.

公开(公告)号：US20230041476A1

公开(公告)日：2023-02-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US20220406398A1

公开(公告)日：2022-12-22

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US11322483B1

公开(公告)日：2022-05-03

申请号：US17090045

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Ken Oowada ,  Mitsuteru Mushiga

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11582 ,  H01L23/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.