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    Systems and methods for last written page handling in a memory device
    37.
    发明授权
    Systems and methods for last written page handling in a memory device 有权
    存储设备中最后一次写入页面处理的系统和方法

    公开(公告)号：US09378810B2

    公开(公告)日：2016-06-28

    申请号：US14192831

    申请日：2014-02-27

    Applicant: SEAGATE TECHNOLOGY, LLC

    Inventor： Zhengang Chen ,  Yu Cai ,  Erich F. Haratsch ,  Zhimin Dong

    IPC: G11C29/00 ,  G11C11/56 ,  G06F11/10 ,  G11C16/28

    CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/28 ,  G11C29/52 ,  G11C2211/5634 ,  G11C2211/5641 ,  H03M13/37

    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

    Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。 在一个实施例中，系统和方法包括提供包括存储器单元的超集的快闪存储器电路，使用标准参考值从一组存储器单元访问数据集，以区分存储器单元组中的位值，并且基于 至少部分地在于确定存储器单元组是最后写入的存储器单元组，使用最后写入的参考值从存储器单元组重新访问数据组以区分存储器单元组中的位值。

    Flash command that reports a count of cell program failures
    38.
    发明授权
    Flash command that reports a count of cell program failures 有权

    公开(公告)号：US10153052B2

    公开(公告)日：2018-12-11

    申请号：US15889536

    申请日：2018-02-06

    Applicant: Seagate Technology LLC

    Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

    IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C29/44 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

    Abstract: An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.

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