公开(公告)号：US20230140748A1

公开(公告)日：2023-05-04

申请号：US17452855

申请日：2021-10-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  KyoungHee Park ,  KyungHwan Kim ,  SeungHyun Lee ,  SangJun Park

IPC: H01Q1/22 ,  H01L23/552 ,  H05K1/18 ,  H05K3/34

Abstract: A semiconductor device has a PCB with an antenna and a semiconductor package mounted onto the PCB. An epoxy molding compound bump is formed or disposed over the PCB opposite the semiconductor package. A first shielding layer is formed over the PCB. A second shielding layer is formed over the semiconductor package. A board-to-board (B2B) connector is disposed on the PCB or as part of the semiconductor package. A conductive bump is disposed between the semiconductor package and PCB.

公开(公告)号：US11616025B2

公开(公告)日：2023-03-28

申请号：US17126621

申请日：2020-12-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L21/033 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.

公开(公告)号：US11610847B2

公开(公告)日：2023-03-21

申请号：US17314916

申请日：2021-05-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  SeongHwan Park ,  JinHee Jung

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L21/48 ,  H01Q1/22

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

公开(公告)号：US20220310408A1

公开(公告)日：2022-09-29

申请号：US17806924

申请日：2022-06-14

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L21/48 ,  H01L23/552 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31 ,  H01L23/544

Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

公开(公告)号：US20200051926A1

公开(公告)日：2020-02-13

申请号：US16529486

申请日：2019-08-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SungWon Cho ,  ChangOh Kim ,  Il Kwon Shim ,  InSang Yoon ,  KyoungHee Park

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/36 ,  H01L23/00

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US20180294236A1

公开(公告)日：2018-10-11

申请号：US16005387

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US20180294235A1

公开(公告)日：2018-10-11

申请号：US16005348

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US09997468B2

公开(公告)日：2018-06-12

申请号：US15091049

申请日：2016-04-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/01029 ,  H01L2224/81

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.