公开(公告)号：US20150097289A1

公开(公告)日：2015-04-09

申请号：US14045640

申请日：2013-10-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L23/528 ,  H01L23/532

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/14 ,  H01L23/522 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

Abstract translation: 本文中呈现的一系列处理步骤用于仅使用一个光刻步骤将光信号路径嵌入纳米线阵列内。 使用所公开的技术，在形成光学特征的同时不需要屏蔽电气特征，反之亦然。 相反，可以在相同的掩蔽周期中基本上同时地创建光学和电信号路径。 这可以通过各个特征的宽度的差异来实现，光信号路径比电的宽度明显更宽。 使用镶嵌工艺，不同宽度的结构镀金属，其过度填充狭窄的沟槽并且填充宽的沟槽。 然后可以将光学包覆材料沉积到沟槽中，以便围绕用于光透射的光学芯。

公开(公告)号：US08900990B2

公开(公告)日：2014-12-02

申请号：US13731878

申请日：2012-12-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Walter Kleemeier ,  Cindy Goldberg

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract translation: 金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。 在电介质层中形成宽沟槽。 导电材料沉积在宽沟槽中。 在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

公开(公告)号：US20140299936A1

公开(公告)日：2014-10-09

申请号：US13856985

申请日：2013-04-04

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device.

Abstract translation: 集成电路器件和制造技术。 半导体器件制造方法可以包括在相同的处理步骤中掺杂集成电路的衬底的第一和第二部分。 第一部分对应于半导体器件的掺杂区域。 第二部分对应于通孔接触。 该方法还可以包括在掺杂之后形成半导体器件的栅极。

公开(公告)号：US20140175610A1

公开(公告)日：2014-06-26

申请号：US13725666

申请日：2012-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L27/02 ,  H01L21/266

CPC classification number: H01L27/0248 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/0255

Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract translation: 可以制造用于保护集成电路免受静电放电的结二极管阵列，以包括各种尺寸的对称和/或非对称结二极管。 二极管可以配置为通过未封装的触点提供低电压和电流放电，或通过封装的触点提供高电压和电流放电。 在制造结二极管阵列中使用倾斜植入物允许使用单个硬掩模来植入多个离子物质。 此外，可以为每个种类以及其他参数（例如，植入能量，植入物掩模厚度和掩模开口的尺寸）选择不同的植入物倾斜角度，以便制造植入区域的形状。 如果需要，可以使用相同的植入物硬掩模，在已经形成的二极管之间插入隔离区域。 可以使用掩埋氧化物层来防止掺杂剂扩散到超过选定深度的衬底中。

公开(公告)号：US12107144B2

公开(公告)日：2024-10-01

申请号：US17574329

申请日：2022-01-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/45 ,  H01L21/265 ,  H01L21/66 ,  H01L21/8238 ,  H01L29/41 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L22/12 ,  H01L29/413 ,  H01L29/456 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4975 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US11205621B2

公开(公告)日：2021-12-21

申请号：US16808090

申请日：2020-03-03

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

公开(公告)号：US10943837B2

公开(公告)日：2021-03-09

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/161 ,  H01L29/423 ,  H01L21/84 ,  H01L21/266 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10816729B2

公开(公告)日：2020-10-27

申请号：US16292047

申请日：2019-03-04

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: G02B6/132 ,  H01L23/522 ,  G02B6/122 ,  G02B6/13 ,  H01L21/768 ,  H01L21/66 ,  G02B6/136 ,  H01L23/532 ,  G02B6/12

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

公开(公告)号：US10680112B2

公开(公告)日：2020-06-09

申请号：US15820010

申请日：2017-11-21

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01J21/10

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

公开(公告)号：US20180158739A1

公开(公告)日：2018-06-07

申请号：US15890001

申请日：2018-02-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/266

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.