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公开(公告)号：US11329067B2
公开(公告)日：2022-05-10
申请号：US16898700
申请日：2020-06-11
Inventor： Jean-Jacques Fagot , Philippe Boivin , Franck Arnaud
IPC: H01L27/12 , H01L21/762 , H01L29/808 , H01L21/84 , H01L27/06
Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
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公开(公告)号：US10707270B2
公开(公告)日：2020-07-07
申请号：US16357152
申请日：2019-03-18
Inventor： Philippe Boivin , Simon Jeannot
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US20200098825A1
公开(公告)日：2020-03-26
申请号：US16566794
申请日：2019-09-10
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe Boivin
Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
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公开(公告)号：US10381344B2
公开(公告)日：2019-08-13
申请号：US15897524
申请日：2018-02-15
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Olivier Weber , Emmanuel Richard , Philippe Boivin
IPC: H01L27/06 , H01L21/84 , H01L27/24 , H01L21/8249 , H01L29/732 , H01L45/00 , H01L29/417 , H01L29/66 , H01L27/12 , H01L29/08
Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
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公开(公告)号：US20180211915A1
公开(公告)日：2018-07-26
申请号：US15700960
申请日：2017-09-11
Inventor： Philippe Boivin , Delia Ristoiu
IPC: H01L23/535 , H01L23/532 , H01L21/768 , H01L27/12
CPC classification number: H01L23/535 , H01L21/76802 , H01L21/76807 , H01L21/76879 , H01L21/76895 , H01L23/485 , H01L23/53257 , H01L27/1203
Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
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Patent Agency Ranking
公开(公告)号：US09941390B2
公开(公告)日：2018-04-10
申请号：US14946408
申请日：2015-11-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe Boivin
IPC: H01L29/66 , H01L27/24 , H01L29/792 , H01L21/225 , H01L29/78 , H01L29/788 , H01L21/02 , H01L21/28 , H01L29/06 , H01L27/108
CPC classification number: H01L29/66666 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/2253 , H01L21/2257 , H01L21/28273 , H01L21/28282 , H01L27/10876 , H01L27/2454 , H01L29/0676 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7883 , H01L29/7889 , H01L29/7926
Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
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公开(公告)号：US09735353B2
公开(公告)日：2017-08-15
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20160380190A1
公开(公告)日：2016-12-29
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
IPC: H01L45/00
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
Abstract translation: 存储单元包括具有控制栅极的选择晶体管和连接到可变电阻元件的第一导电端子。 存储单元形成在包括被第一绝缘层覆盖的半导体衬底的晶片中，绝缘层被由半导体制成的有源层覆盖。 栅极形成在有源层上，并具有用第二绝缘层覆盖的侧面。 可变电阻元件包括覆盖有源层的横向侧面的第一层，该沟槽沿着栅极的侧面通过有源层形成并且到达第一绝缘层的沟槽，以及由可变电阻材料制成的第二层 。
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公开(公告)号：US09196654B2
公开(公告)日：2015-11-24
申请号：US14150592
申请日：2014-01-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe Boivin
IPC: H01L27/24 , H01L29/66 , H01L29/792 , H01L29/78 , H01L29/788 , H01L27/108
CPC classification number: H01L29/66666 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/2253 , H01L21/2257 , H01L21/28273 , H01L21/28282 , H01L27/10876 , H01L27/2454 , H01L29/0676 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7883 , H01L29/7889 , H01L29/7926
Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
Abstract translation: 本发明涉及一种制造垂直MOS晶体管的方法，包括以下步骤：在半导体表面之上形成至少一个电介质层中的导电层; 通过至少导电层蚀刻孔，所述孔暴露所述导电层的内侧边缘和所述半导体表面的一部分; 在导电层的内侧边缘上形成栅极氧化物，在半导体表面的部分上形成底部氧化物; 在所述孔的侧边缘上形成蚀刻保护侧壁，所述侧壁覆盖所述栅极氧化物和所述底部氧化物的外部区域，留下所述底部氧化物的内部区域; 蚀刻底部氧化物的暴露的内部区域，直到达到半导体表面; 以及在所述孔中沉积半导体材料。
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公开(公告)号：US11957067B2
公开(公告)日：2024-04-09
申请号：US17328917
申请日：2021-05-24
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004 , G11C2213/79 , G11C2213/82
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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