公开(公告)号：US10998322B2

公开(公告)日：2021-05-04

申请号：US16295562

申请日：2019-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L27/108

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US20210082799A1

公开(公告)日：2021-03-18

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L27/108 ,  G11C5/10

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US10714565B2

公开(公告)日：2020-07-14

申请号：US16593438

申请日：2019-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-hyung Nam ,  Bong-Soo Kim ,  Yoosang Hwang

IPC: H01L29/41 ,  H01L49/02 ,  H01L27/108 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/112

Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

公开(公告)号：US10580469B2

公开(公告)日：2020-03-03

申请号：US16460284

申请日：2019-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C11/00 ,  G11C5/02 ,  G11C14/00 ,  H01L27/108 ,  H01L45/00 ,  H01L27/24 ,  H01L49/02 ,  H01L23/528

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US10559571B2

公开(公告)日：2020-02-11

申请号：US15952350

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Semyeong Jang ,  Yoosang Hwang

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/768 ,  B08B7/00

Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

公开(公告)号：US20190051652A1

公开(公告)日：2019-02-14

申请号：US15952308

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US20190027482A1

公开(公告)日：2019-01-24

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGWOO KIM ,  Bong-soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24

CPC classification number: H01L27/10897 ,  G11C11/005 ,  G11C14/0045 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US20180308849A1

公开(公告)日：2018-10-25

申请号：US16021573

申请日：2018-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/10814 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/76224 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53261 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second contact structure on the bit line structure and spaced apart from the first contact structure across the bit line structure, and an insulation pattern between the bit line structure and the first contact structure. The second contact structure covers at least a portion of a top surface of the bit line structure. The insulation pattern comprises a protrusion that protrudes from a sidewall of the insulation pattern that immediately adjacent to the bit line structure. The protrusion protrudes in a first direction parallel to a top surface of the substrate.

公开(公告)号：US09935111B2

公开(公告)日：2018-04-03

申请号：US15631105

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Sohyun Park ,  Bong-Soo Kim ,  Yoosang Hwang ,  Dong-Wan Kim ,  Junghoon Han

IPC: H01L21/20 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

公开(公告)号：US20180040560A1

公开(公告)日：2018-02-08

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/2436 ,  H01L27/2463

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.