公开(公告)号：US11550498B2

公开(公告)日：2023-01-10

申请号：US17030635

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

IPC: G06F3/06 ,  G06K9/62

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

公开(公告)号：USD973080S1

公开(公告)日：2022-12-20

申请号：US29778611

申请日：2021-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Jangwoo Lee ,  Seoeun Park ,  Yongho Kim

公开(公告)号：US11196304B2

公开(公告)日：2021-12-07

申请号：US16564086

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangwoo Lee ,  Taeseon Kim ,  Taeho Wang ,  Soonkyu Jang ,  Sunmi Jin ,  Jihoon Ha

IPC: H02J50/80 ,  H04B5/00 ,  H02J50/40 ,  H02J50/10 ,  H02J7/02

Abstract: According to certain embodiments, an electronic device comprises a plurality of coils configured to transmit charging power; a communication circuit; at least one processor; and at least one memory. The at least one memory stores instructions that, when executed by the at least one processor, causes the at least one processor to perform a plurality of operations. The plurality of operations comprises transmitting a first signal for requesting device-related information to a plurality of external electronic devices through the communication circuit, receiving a corresponding plurality of first response signals in response to the first signal from the plurality of external electronic devices through the communication circuit, selecting at least one external electronic device from among the plurality of external electronic devices on the basis of the plurality of first response signals, and upon selecting the at least one selected external electronic device, transmitting a second signal that indicates the at least one selected external electronic device and comprises at least information associated with the plurality of external electronic devices to the plurality of external electronic devices via the communication circuit.

公开(公告)号：US11107512B2

公开(公告)日：2021-08-31

申请号：US17001941

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Jeong ,  Kyungtae Kang ,  Jangwoo Lee ,  Jeongdon Ihm

IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US11080218B2

公开(公告)日：2021-08-03

申请号：US16425105

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjae Yang ,  Jangwoo Lee ,  Hwasuk Cho ,  Jeongdon Ihm

IPC: G06F13/16 ,  G11C7/10 ,  G06F3/06 ,  G11C8/12 ,  G11C5/04 ,  G11C8/06 ,  G11C16/06 ,  G11C16/08

Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

公开(公告)号：US09881679B2

公开(公告)日：2018-01-30

申请号：US15461241

申请日：2017-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangwoo Lee ,  Kyoungtae Kang ,  Taesung Lee ,  Jeongdon Ihm

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

公开(公告)号：US08940584B2

公开(公告)日：2015-01-27

申请号：US14272681

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk Kim ,  Jangwoo Lee ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L21/44 ,  H01L23/06 ,  H01L23/10 ,  H01L23/31 ,  H01L23/552 ,  H01L23/498 ,  H01L21/56 ,  H01L23/34 ,  H01L25/065 ,  H01L23/36 ,  H01L23/42

CPC classification number: H01L23/06 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/16251 ,  H01L2924/00

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract translation: 一种半导体封装，包括具有芯片安装区域和周边区域的封装基板，并且包括形成在周边区域中的接地层，在芯片安装区域中的封装基板上的第一焊球，接地层上的第二焊球，至少 可以提供在芯片安装区域中堆叠在封装基板上的一个半导体芯片，以及覆盖半导体芯片并且在周边区域中与封装基板接触的封装帽。 封装帽电连接到第二焊球。 还提供了制造半导体封装的方法。