公开(公告)号：US20180197586A1

公开(公告)日：2018-07-12

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

CPC classification number: G11C8/08 ,  G06F13/4072 ,  G11C5/06 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08 ,  H01L27/112 ,  H01L27/11575 ,  H01L27/11582

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

公开(公告)号：US20180122904A1

公开(公告)日：2018-05-03

申请号：US15458200

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

公开(公告)号：US09859363B2

公开(公告)日：2018-01-02

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES, LLC.

Inventor： Zhenyu Lu ,  Kota Funayama ,  Chun-Ming Wang ,  Jixin Yu ,  Chenche Huang ,  Tong Zhang ,  Daxin Mao ,  Johann Alsmeier ,  Makoto Yoshida ,  Lauren Matsumoto

IPC: H01L29/06 ,  H01L21/76 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/112

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.