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    NAND boosting using dynamic ramping of word line voltages
    31.
    发明授权
    NAND boosting using dynamic ramping of word line voltages 有权

    公开(公告)号：US10297329B2

    公开(公告)日：2019-05-21

    申请号：US15352390

    申请日：2016-11-15

    Applicant: SanDisk Technologies LLC

    Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

    IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

    Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

    Reversible resistivity memory with crystalline silicon bit line
    33.
    发明授权
    Reversible resistivity memory with crystalline silicon bit line 有权

    公开(公告)号：US09685484B1

    公开(公告)日：2017-06-20

    申请号：US15215263

    申请日：2016-07-20

    Applicant: SanDisk Technologies LLC

    Inventor： Peter Rabkin ,  Perumal Ratnam ,  Masaaki Higashitani ,  Chris Petti

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

    Abstract: Technology is described for reversible resistivity memory having a crystalline silicon bit line. In one aspect, a memory structure comprises a hollow pillar of crystalline silicon inside of reversible resistivity material. The crystalline silicon may serve as a bit line. The memory structure may further comprise conductive material that forms word lines coupled to the outer surface of the reversible resistivity material. A memory cell comprises a portion of the reversible resistivity material between the crystalline silicon and one of the word lines. In one aspect, the hollow pillar of crystalline silicon surrounds a gate oxide, which surrounds a conductive transistor gate. Thus, the hollow pillar of crystalline silicon may function as a channel of a transistor. In one aspect, the crystalline silicon has predominantly a (100) orientation with respect to an inner surface of the reversible resistivity material. In one aspect, the crystalline silicon is a single crystal.

    Three-dimensional memory device with vertical field effect transistors and method of making thereof
    38.
    发明授权
    Three-dimensional memory device with vertical field effect transistors and method of making thereof 有权

    公开(公告)号：US11569215B2

    公开(公告)日：2023-01-31

    申请号：US17007823

    申请日：2020-08-31

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kwang-Ho Kim ,  Peter Rabkin

    IPC: H01L25/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

    Semiconductor die containing silicon nitride stress compensating regions and method for making the same
    40.
    发明授权
    Semiconductor die containing silicon nitride stress compensating regions and method for making the same 有权

    公开(公告)号：US11430745B2

    公开(公告)日：2022-08-30

    申请号：US16806087

    申请日：2020-03-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

    IPC: H01L23/00 ,  H01L25/065 ,  H01L21/02

    Abstract: A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam. A first subset of the silicon nitride material portions that is not irradiated with the laser beam includes first silicon nitride material portions that apply tensile stress to respective surrounding material portions, and the second subset of the silicon nitride material portions that is irradiated with the laser beam includes second silicon nitride material portions that apply compressive stress to respective surrounding material portions.

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