公开(公告)号：US20100239895A1

公开(公告)日：2010-09-23

申请号：US12310604

申请日：2007-08-25

Applicant: Seung-Jin Yang ,  Jeong Hee Choi ,  Hanho Lee ,  Ji Heon Ryu

Inventor： Seung-Jin Yang ,  Jeong Hee Choi ,  Hanho Lee ,  Ji Heon Ryu

IPC: H01M2/12

CPC classification number: H01M2/1235 ,  H01M2/0207 ,  H01M2/0275 ,  H01M2/0277 ,  H01M2/0285 ,  H01M2/0287 ,  H01M2/08 ,  H01M2/1229 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0583 ,  H01M10/0585

Abstract: Disclosed herein is a plate-shaped secondary battery constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case, and the battery case is sealed by thermal welding, wherein the secondary battery has at least one valve (one-way exhaust valve), having a small thickness, mounted at a sealed portion, formed at the outer circumference of an electrode assembly receiving part of the battery case, for allowing internal high-pressure gas to be exhausted out of a battery cell and preventing external gas from being introduced into the battery cell. The secondary battery according to the present invention has the effect of effectively exhausting internal high-pressure gas generated during the abnormal operation of the battery, such as overcharge, out of the battery case, while maintaining the sealability of the battery case, thereby simultaneously improving the efficiency and safety of the battery.

Abstract translation: 这里公开了一种板状二次电池，其结构是将阴极/隔板/阳极结构的电极组件安装在电池壳体中，并且电池壳体通过热焊接而被密封，其中二次电池具有至少 一个安装在密封部分的具有小厚度的阀（单向排气阀），形成在电池组件的电极组件接收部分的外周处，用于允许内部高压气体从 并且防止外部气体被引入电池单体。 根据本发明的二次电池具有在保持电池壳体的密封性的同时有效地排出在电池异常操作期间产生的内部高压气体（例如过充电）从电池壳体中排出的效果，从而同时改善 电池的效率和安全性。

公开(公告)号：US20100028772A1

公开(公告)日：2010-02-04

申请号：US12309912

申请日：2007-07-21

Applicant: Seung-Jin Yang ,  Jeong Hee Choi ,  Han-Ho Lee ,  Ji Heon Ryu

Inventor： Seung-Jin Yang ,  Jeong Hee Choi ,  Han-Ho Lee ,  Ji Heon Ryu

IPC: H01M2/02

CPC classification number: H01M2/021 ,  H01M2/0275 ,  H01M2/345 ,  H01M10/052

Abstract: Disclosed herein is a secondary battery including an electrode assembly of a cathode/separator/anode structure mounted in a pouch-shaped battery case in a sealed state, wherein a residue portion, which is not sealed (non-sealing residue portion), is defined between a sealing portion of the battery case and the electrode assembly for collecting generated gas, and the non-sealing residue portion is formed by mounting the electrode assembly between upper and lower laminate sheets, at least one of which has a receiving part of a size approximately corresponding to the electrode assembly, sealing three sides of the upper and lower laminate sheets, including two sides where electrode terminals are disposed, among four sides of the upper and lower laminate sheets, injecting an electrolyte in the battery case through the non-sealing portion, and sealing the non-sealing portion such that the resultant sealing portion is spaced a predetermined width from the receiving part.

Abstract translation: 本文公开了一种二次电池，其包括以密封状态安装在袋状电池壳体中的阴极/隔板/阳极结构的电极组件，其中限定未密封（非密封残留部分）的残留部分 在电池壳体的密封部分和用于收集产生的气体的电极组件之间，并且非密封残留部分通过将电极组件安装在上部和下部层压片材之间而形成，其中至少一个具有容纳部分的尺寸 大致对应于电极组件，在上下层叠片的四个侧面之间密封上下层叠片的三面，包括设置有电极端子的两侧，通过非密封将电解质注入电池壳体 并且密封非密封部分，使得所得密封部分与接收部分间隔开预定宽度。

公开(公告)号：US20100001328A1

公开(公告)日：2010-01-07

申请号：US12498724

申请日：2009-07-07

Applicant: Seung-Jin Yang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Yong-Suk Choi ,  Bae-Seong Kwon

Inventor： Seung-Jin Yang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Yong-Suk Choi ,  Bae-Seong Kwon

IPC: H01L27/105 ,  H01L29/40 ,  H01L27/108 ,  H01L29/792

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L27/11526 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/85375 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer.

Abstract translation: 公开了一种具有防焊垫剥离结构的焊盘。 在形成接合焊盘的方法中，在形成金属焊盘层之后，在金属焊盘层中形成狭缝。 在金属垫层上形成保护层。 部分去除保护层以露出金属垫，使得保护层的一部分保留在狭缝中以连接到主保护层。 形成在狭缝中的保护层连接到保护层，使得当产生物理冲击时残留保护层图案缓冲，以防止金属垫层的剥离。

公开(公告)号：US07642593B2

公开(公告)日：2010-01-05

申请号：US11698658

申请日：2007-01-26

Applicant: Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

Inventor： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC: H01L21/336

CPC classification number: H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Abstract translation: 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

公开(公告)号：US07495281B2

公开(公告)日：2009-02-24

申请号：US11488983

申请日：2006-07-19

Applicant: Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

Inventor： Seung-Jin Yang ,  Jeong-Uk Han ,  Kwang-Wook Koh ,  Jae-Hwang Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC: H01L29/788

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract translation: 在非易失性存储器件及其形成和操作它的方法中，当浮置栅极和控制栅极堆叠时，一个存储器晶体管包括覆盖浮置栅极的两个侧壁的侧壁选择栅极。 侧壁选择门是间隔件形式。 由于侧壁选择栅极在浮动栅极的侧壁上是间隔物形式，所以可以提高电池的集成度。 此外，由于侧壁选择栅极设置在浮置栅极的两个侧壁上，所以可以控制从位线和公共源极线施加的电压，因此可以防止常规的写入/擦除错误。 因此，可以提高阈值电压的分布。

公开(公告)号：US07411243B2

公开(公告)日：2008-08-12

申请号：US11214247

申请日：2005-08-29

Applicant: Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

Inventor： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

IPC: H01L29/76 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7881

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Abstract translation: 提供一种非易失性半导体器件及其制造方法。 非易失性半导体器件包括形成在基板上的半导体本体，该半导体本体在一个方向上被延伸并且具有垂直于基板的主表面和细长方向的横截面，该横截面具有预定的曲率， 设置在沟道区域上的隧道绝缘层，设置在隧道绝缘层上并与沟道区电绝缘的浮置栅极，设置在浮动栅极上的栅极间绝缘层，设置在栅极上的控制栅极 绝缘层和与浮置栅极电绝缘的源极和漏极区域，其与控制栅极的两侧对准并形成在半导体本体内。

公开(公告)号：US20070158737A1

公开(公告)日：2007-07-12

申请号：US11646165

申请日：2006-12-27

Applicant: Seung-Jin Yang ,  Jeong-Uk Han

Inventor： Seung-Jin Yang ,  Jeong-Uk Han

IPC: H01L29/788 ,  H01L21/336

CPC classification number: G11C17/12 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11246 ,  H01L27/11253 ,  H01L27/1126 ,  H01L27/11286 ,  H01L27/11293 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546

Abstract: A mask read only memory (ROM) device includes a plurality of isolation patterns disposed at predetermined regions of a semiconductor substrate to define a plurality of active regions. The semiconductor substrate includes a mask ROM region where a plurality of on cells and a plurality of off-cells are disposed. The mask ROM further includes a plurality of gate lines disposed over the active regions, and which cross over the isolation patterns, a plurality of gate insulating layers interposed between the gate lines and the active regions and a floating conductive pattern and a inter-gate dielectric pattern located between the gate line and the gate insulating layer of the off-cell.

Abstract translation: 掩模只读存储器（ROM）器件包括设置在半导体衬底的预定区域以限定多个有源区的多个隔离图案。 半导体衬底包括掩模ROM区域，其中设置有多个接通单元和多个非接线盒。 掩模ROM还包括设置在有源区上方并且跨越隔离图案的多个栅极线，插入在栅极线和有源区之间的多个栅极绝缘层以及浮置导电图案和栅极间电介质 位于离子电池的栅极线和栅极绝缘层之间的图案。

公开(公告)号：US20060043469A1

公开(公告)日：2006-03-02

申请号：US11124716

申请日：2005-05-09

Applicant: Young-Sam Park ,  Seung-Beom Yoon ,  Seung-Jin Yang

Inventor： Young-Sam Park ,  Seung-Beom Yoon ,  Seung-Jin Yang

IPC: H01L29/792

CPC classification number: H01L29/78 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7923

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and a method of forming the same are disclosed. The SONOS memory cell includes a substrate in which a recessed region having at least one side wall is arranged and a trap storage pattern with which the recessed region is filled with a first insulating film is interposed. A control gate electrode is arranged on the top surface of the substrate and the top surface of the trap storage pattern with a second insulating film interposed. First and second source/drain regions are arranged in the substrate on both sides of the control gate electrode. The top surface of the trap storage pattern is flat and is at least as high as the top surface of the substrate.

Abstract translation: 公开了一种氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储单元及其形成方法。 SONOS存储单元包括其中布置有具有至少一个侧壁的凹陷区域的基板，并且插入有凹陷区域填充有第一绝缘膜的陷阱存储图案。 控制栅电极设置在基板的顶表面和陷阱存储图案的顶表面上，并插入第二绝缘膜。 第一和第二源极/漏极区域布置在控制栅电极两侧的衬底中。 阱存储图案的顶表面是平坦的并且至少与衬底的顶表面一样高。