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    Nonvolatile memory device and method of fabricating the same
    3.
    发明申请
    Nonvolatile memory device and method of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20070170491A1

    公开(公告)日：2007-07-26

    申请号：US11698658

    申请日：2007-01-26

    申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

    摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

    摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

    Nonvolatile memory device and method of fabricating the same
    5.
    发明授权
    Nonvolatile memory device and method of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US07642593B2

    公开(公告)日：2010-01-05

    申请号：US11698658

    申请日：2007-01-26

    申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

    摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

    摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

    Methods of manufacturing non-volatile memory devices having a vertical channel
    8.
    发明授权
    Methods of manufacturing non-volatile memory devices having a vertical channel 有权
    制造具有垂直通道的非易失性存储器件的方法

    公开(公告)号：US07820516B2

    公开(公告)日：2010-10-26

    申请号：US11798563

    申请日：2007-05-15

    申请人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

    发明人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0692 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

    摘要： Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

    摘要翻译： 公开了一种半导体闪存单元，包括形成在半导体衬底中的第一和第二源极线，从源极线之间的衬底延伸的半导体柱，形成在半导体柱的相对侧表面上并由沟槽分隔的第一和第二电荷存储结构 隔离结构。 选择分离存储单元阵列中的相邻半导体柱的x和y间距，由此形成沟槽隔离结构用于分离电荷存储结构和设置在半导体柱的相对侧上的导电结构。 还公开了制造这种结构的方法，由此可以提高闪存器件，特别是NOR闪存器件的密度。

    Non-volatile memory devices having a vertical channel and methods of manufacturing such devices
    9.
    发明申请
    Non-volatile memory devices having a vertical channel and methods of manufacturing such devices 有权
    具有垂直通道的非易失性存储器件和制造这种器件的方法

    公开(公告)号：US20080002475A1

    公开(公告)日：2008-01-03

    申请号：US11798563

    申请日：2007-05-15

    申请人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

    发明人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

    IPC分类号： G11C11/34 ,  H01L21/336

    CPC分类号： H01L29/0692 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

    摘要： Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

    摘要翻译： 公开了一种半导体闪存单元，包括形成在半导体衬底中的第一和第二源极线，从源极线之间的衬底延伸的半导体柱，形成在半导体柱的相对侧表面上并由沟槽分隔的第一和第二电荷存储结构 隔离结构。 选择分离存储单元阵列中的相邻半导体柱的x和y间距，由此形成沟槽隔离结构用于分离电荷存储结构和设置在半导体柱的相对侧上的导电结构。 还公开了制造这种结构的方法，由此可以提高闪存器件，特别是NOR闪存器件的密度。

    Nonvolatile semiconductor device and method of fabricating the same
    10.
    发明授权
    Nonvolatile semiconductor device and method of fabricating the same 有权
    非易失性半导体器件及其制造方法

    公开(公告)号：US07514739B2

    公开(公告)日：2009-04-07

    申请号：US11687942

    申请日：2007-03-19

    申请人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

    发明人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L29/7854 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7881

    摘要： A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.

    摘要翻译： 堆叠型非易失性半导体器件包括：形成在基板上的存储器件，该存储器件包括在一个方向上延伸的半导体本体，具有垂直于主表面的横截面，具有预定曲率，半导体本体上沿着圆周的沟道区域， 沟道区域上的隧道绝缘层，与沟道区绝缘的隧道绝缘层上的浮动栅极，浮置栅极上的高介电常数材料层，高介电常数材料层上的金属控制栅极，绝缘层 浮置栅极，与半导体主体上的金属控制栅极相邻的源极和漏极区域，存储器件上的绝缘层和绝缘层上的导电层，以及形成在导电层上的存储器件，包括 具有垂直于主表面的横截面在一个方向上延伸的半导体本体，具有预制件 沿着半导体本体的圆周的通道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的浮动栅极，与沟道区电绝缘，浮置栅极上的高介电常数材料层， 在高介电常数材料层上的金属控制栅极，与浮动栅极绝缘，以及与金属控制栅极相邻的源极和漏极区域。