MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test
    31.
    发明授权
    MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test 有权
    MOS测试结构,用于形成MOS测试结构的方法和用于进行晶片验收测试的方法

    公开(公告)号:US08816715B2

    公开(公告)日:2014-08-26

    申请号:US13105913

    申请日:2011-05-12

    摘要: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

    摘要翻译: 公开了MOS测试结构。 划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。 外延层设置在第一侧上,掺杂阱设置在外延层上,并且掺杂区域设置在掺杂阱上。 第一深度的沟槽栅极设置在掺杂区域,掺杂阱和划线区域中。 导电材料填充测试,通过该测试具有覆盖测试通孔的内壁的第二深度和隔离,并且设置在掺杂区域,掺杂阱,外延层和划线区域中,以电连接 到外延层,使得测试通孔能够一起测试外延层和衬底。

    Trench MOS structure and method for making the same
    32.
    发明授权
    Trench MOS structure and method for making the same 有权
    沟槽MOS结构和制作方法

    公开(公告)号:US08692318B2

    公开(公告)日:2014-04-08

    申请号:US13104924

    申请日:2011-05-10

    IPC分类号: H01L29/66

    摘要: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

    摘要翻译: 提供沟槽MOS结构。 沟槽MOS结构包括保护环内的衬底,外延层,沟槽,栅极隔离,沟槽栅极,保护环和加强结构。 衬底具有第一导电类型,第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 沟槽设置在外延层中。 栅极隔离覆盖沟槽的内壁。 沟槽栅设置在沟槽中并且具有第一导电类型。 保护环具有第二导电类型并且设置在外延层内。 加强结构具有电绝缘材料并且设置在保护环内。

    Post-CMP wafer cleaning apparatus
    33.
    发明授权
    Post-CMP wafer cleaning apparatus 有权
    CMP后晶圆清洗装置

    公开(公告)号:US08458842B2

    公开(公告)日:2013-06-11

    申请号:US13104964

    申请日:2011-05-10

    IPC分类号: B08B3/02

    摘要: A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.

    摘要翻译: CMP后晶片清洗装置包括:腔室; 多个辊子,适于在所述腔室内保持和旋转晶片; 至少一个刷子,适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置,所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。

    Method for obtaining a layout design for an existing integrated circuit
    34.
    发明授权
    Method for obtaining a layout design for an existing integrated circuit 有权
    获得现有集成电路布局设计的方法

    公开(公告)号:US08394721B2

    公开(公告)日:2013-03-12

    申请号:US13104986

    申请日:2011-05-11

    IPC分类号: H01L21/311

    摘要: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

    摘要翻译: 一种用于获得现有集成电路的布局设计的方法,其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面,并且获得倾斜抛光表面的一个或多个图像。 图像可以直接重叠,或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

    METHOD OF FORMING CONDUCTIVE PATTERN
    35.
    发明申请
    METHOD OF FORMING CONDUCTIVE PATTERN 有权
    形成导电图案的方法

    公开(公告)号:US20130052820A1

    公开(公告)日:2013-02-28

    申请号:US13214244

    申请日:2011-08-22

    IPC分类号: H01L21/28

    摘要: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.

    摘要翻译: 提供形成导电图案的方法。 在底层上形成接种层。 通过使用能量射线,对接种层的表面的一部分进行照射处理。 因此,接种层包括多个照射区域和多个未照射区域。 对接种层的照射区域进行转化处理。 进行选择性生长处理,以在接种层的每个未照射区域上形成导电图案。 去除接种层的照射区域,使得导电图案彼此绝缘。

    Method of reducing microloading effect
    36.
    发明授权
    Method of reducing microloading effect 有权
    降低微载荷效应的方法

    公开(公告)号:US08377632B2

    公开(公告)日:2013-02-19

    申请号:US13118447

    申请日:2011-05-29

    IPC分类号: G03F7/26

    CPC分类号: H01L21/3083

    摘要: The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.

    摘要翻译: 本发明提供一种通过使用光致抗蚀剂层作为缓冲液来减少微载物效应的方法。 该方法包括:提供限定有致密区域和隔离区域的衬底。 然后,分别在密集区域和孤立区域上形成致密特征图案和隔离特征图案。 之后,形成光致抗蚀剂层以覆盖隔离区域。 最后,通过将密集特征图案和孤立的特征图案作为掩模来蚀刻基底和光致抗蚀剂层。

    METHOD FOR FORMING OPENINGS IN SEMICONDUCTOR DEVICE
    37.
    发明申请
    METHOD FOR FORMING OPENINGS IN SEMICONDUCTOR DEVICE 有权
    在半导体器件中形成开口的方法

    公开(公告)号:US20130017687A1

    公开(公告)日:2013-01-17

    申请号:US13183358

    申请日:2011-07-14

    IPC分类号: H01L21/306

    摘要: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

    摘要翻译: 提供了一种在半导体器件中形成开口的方法,包括:向半导体衬底提供其上顺序形成的氧化硅层,多晶硅层和氮化硅层; 图案化氮化硅层,在氮化硅层中形成第一开口,其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢(HBr),氧(O 2)和碳氟化合物(C x F y)的气体蚀刻剂进行第一蚀刻工艺,在多晶硅层中形成第二开口,其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面,其中x在1-5之间,y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺,在由所述第二开口暴露的所述氧化硅层中形成第三开口。

    Method of inspecting memory cell
    38.
    发明授权
    Method of inspecting memory cell 有权
    检查记忆体的方法

    公开(公告)号:US08335119B1

    公开(公告)日:2012-12-18

    申请号:US13276952

    申请日:2011-10-19

    IPC分类号: G11C7/00

    摘要: A method of inspecting a memory cell is provided, including: providing a semiconductor substrate with a capacitor formed therein and a transistor formed thereon, wherein the transistor is electrically connected to the capacitor; inspecting a size of a top surface of the capacitor and a pitch between the capacitor and the transistor electrically connected thereto by an optical measuring system, thereby obtaining a first measurement data and a second measurement data; and comparing the first and second measurement data with designed specifications of the capacitor and transistor, thereby determining functionality of the memory cell comprising the capacitor and the transistor.

    摘要翻译: 提供了一种检查存储单元的方法,包括:提供其中形成有电容器的半导体衬底和形成在其上的晶体管,其中晶体管电连接到电容器; 通过光学测量系统检查电容器的顶表面的大小和电容器与与其电连接的晶体管之间的间距,从而获得第一测量数据和第二测量数据; 以及将第一和第二测量数据与电容器和晶体管的设计规范进行比较,从而确定包括电容器和晶体管的存储单元的功能。

    CHEMICAL MECHANICAL POLISHING SYSTEM
    39.
    发明申请
    CHEMICAL MECHANICAL POLISHING SYSTEM 有权
    化学机械抛光系统

    公开(公告)号:US20120289133A1

    公开(公告)日:2012-11-15

    申请号:US13106822

    申请日:2011-05-12

    IPC分类号: B24B55/00

    摘要: A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface.

    摘要翻译: 化学机械抛光(CMP)系统包括生产所用浆料的晶片抛光单元; 用于接收和处理所使用的浆料从而产生提取的碱性溶液的浆料处理系统; 以及利用所提取的碱性溶液洗涤抛光的晶片表面的后CMP清洁单元。 后CMP清洁单元包括用于支撑和旋转晶片的多个辊,用于洗涤晶片的刷子和布置在刷子附近的喷杆,用于将提取的碱性溶液喷射到抛光的晶片表面上。

    OPTICAL LENS AND OPTICAL MICROSCOPE SYSTEM USING THE SAME
    40.
    发明申请
    OPTICAL LENS AND OPTICAL MICROSCOPE SYSTEM USING THE SAME 审中-公开
    光学透镜和光学显微镜系统

    公开(公告)号:US20120287500A1

    公开(公告)日:2012-11-15

    申请号:US13106864

    申请日:2011-05-13

    IPC分类号: G02B21/02 G02B3/02

    CPC分类号: G02B5/005 G02B21/02

    摘要: An optical lens is provided in the present invention. The optical lens includes a first curved surface and an annular mask component on and in direct contact with the first curved surface, wherein the annular mask component shields a peripheral annular region of the optical lens from entry of light. The present invention further provides an optical microscope system using the same.

    摘要翻译: 在本发明中提供了一种光学透镜。 光学透镜包括在第一弯曲表面上且与第一弯曲表面直接接触的第一弯曲表面和环形掩模部件,其中环形掩模部件屏蔽光学透镜的外围环形区域以防止光入射。 本发明还提供一种使用其的光学显微镜系统。