公开(公告)号：US5675168A

公开(公告)日：1997-10-07

申请号：US415928

申请日：1995-04-03

申请人： Kyoji Yamashita ,  Shinji Odanaka ,  Kazumi Kurimoto ,  Akira Hiroki ,  Isao Miyanaga ,  Atsushi Hori

发明人： Kyoji Yamashita ,  Shinji Odanaka ,  Kazumi Kurimoto ,  Akira Hiroki ,  Isao Miyanaga ,  Atsushi Hori

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L23/60

CPC分类号： H01L27/0266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/7835 ,  H01L2924/0002

摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.

摘要翻译： 公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。 表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

公开(公告)号：US08260031B2

公开(公告)日：2012-09-04

申请号：US12347345

申请日：2008-12-31

申请人： Kyoji Yamashita

发明人： Kyoji Yamashita

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G06T2207/30148

摘要： A pattern inspection apparatus includes a magnification conversion unit to convert first sample optical image data to higher resolution second sample optical image data, a low-pass filter configured to filter first design image data which has a resolution N times that of the first sample optical image data, an optical filter which calculates third design image data by convolving the second design image data with an optical model function, a coefficient acquisition unit configured to acquire a coefficient of the predetermined optical model function using the second sample optical image data and the third design image data, an optical image acquisition unit configured to acquire actual optical image data of an inspection target workpiece, a reference image data generation unit configured to generate reference image data corresponding to the actual optical image data, and a comparison unit configured to compare the actual optical image data with the reference image data.

摘要翻译： 图案检查装置包括：倍率转换单元，用于将第一样本光学图像数据转换为更高分辨率的第二样本光学图像数据;低通滤波器，被配置为对具有第一样本光学图像的分辨率的N倍的第一设计图像数据进行滤波 数据，光滤波器，其通过利用光学模型函数卷积第二设计图像数据来计算第三设计图像数据;系数获取单元，被配置为使用第二样本光学图像数据和第三设计来获取预定光学模型函数的系数 图像数据，被配置为获取检查对象工件的实际光学图像数据的光学图像获取单元，被配置为生成与实际光学图像数据相对应的参考图像数据的参考图像数据生成单元，以及比较单元， 具有参考图像数据的光学图像数据。

公开(公告)号：US07519593B2

公开(公告)日：2009-04-14

申请号：US11553711

申请日：2006-10-27

申请人： Kazuko Abe ,  Junichi Yamamoto ,  Rei Yano ,  Masataka Yamada ,  Yasuhide Kurosaki ,  Michiyo Ikegami ,  Kyoji Yamashita ,  Kouji Gouda

发明人： Kazuko Abe ,  Junichi Yamamoto ,  Rei Yano ,  Masataka Yamada ,  Yasuhide Kurosaki ,  Michiyo Ikegami ,  Kyoji Yamashita ,  Kouji Gouda

IPC分类号： G06F7/00 ,  G06F17/30 ,  G06F12/00

CPC分类号： G06F17/30964 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99953

摘要： A data searching unit 12 of a data searching apparatus 10 Obtains, according to a searching request including a search condition specified by a data searching application 16, metadata which satisfy the search condition from a data storage unit 11, and instructs an external communication unit 15 to request searching of data to a data providing apparatus 20 with the same search condition.

摘要翻译： 数据搜索装置10的数据搜索单元12根据包括由数据搜索应用16指定的搜索条件的搜索请求，从数据存储单元11获得满足搜索条件的元数据，并指示外部通信单元15 请求搜索具有相同搜索条件的数据提供装置20。

公开(公告)号：US20080166054A1

公开(公告)日：2008-07-10

申请号：US12040541

申请日：2008-02-29

申请人： Hideo Tsuchiya ,  Kyoji Yamashita ,  Toshiyuki Watanabe ,  Ikunao Isomura ,  Toru Tojo ,  Yasushi Sanada

发明人： Hideo Tsuchiya ,  Kyoji Yamashita ,  Toshiyuki Watanabe ,  Ikunao Isomura ,  Toru Tojo ,  Yasushi Sanada

IPC分类号： G06K9/46

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： A pattern inspection apparatus uses a die-to-database comparison method which compares detected pattern data obtained from an optical image of a pattern of a plate to be inspected with first reference pattern data obtained from designed pattern data in combination with a die-to-die comparison method which compares the detected pattern data with second reference pattern data obtained by detecting an area to be a basis for repetition. A computer detects presence of a plurality of repeated pattern areas from layout information contained in the designed pattern data, reads the arrangement, the number, the dimension and the repeated pitch of the repeated pattern areas, and automatically fetches an inspection area of the die-to-die comparison method.

摘要翻译： 图案检查装置使用芯片对数据库比较方法，将从被检查板的图案的光学图像获得的检测图案数据与从设计图案数据获得的第一参考图案数据结合， 芯片比较方法，其将检测到的图案数据与通过检测作为重复基础的区域获得的第二参考图案数据进行比较。 计算机从包含在设计图案数据中的布局信息中检测多个重复图案区域的存在，读取重复图案区域的布置，数量，尺寸和重复间距，并且自动取出模具数据的检查区域， 对比方法。

公开(公告)号：US07230435B2

公开(公告)日：2007-06-12

申请号：US10760449

申请日：2004-01-21

申请人： Tatsuya Kunikiyo ,  Tetsuya Watanabe ,  Toshiki Kanamoto ,  Kyoji Yamashita

发明人： Tatsuya Kunikiyo ,  Tetsuya Watanabe ,  Toshiki Kanamoto ,  Kyoji Yamashita

IPC分类号： G01R27/26 ,  G01R27/02

CPC分类号： G01R27/2605

摘要： A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N1) is electrically connected to a terminal (P2) between the drains of PMOS and NMOS transistors (MP2, MN2). As a target capacitance forming part, a coupling capacitance (Cc) is formed between the node (N1) and a node (N2). The node (N2) is connected to a pad (58) through the terminal (P2) and an NMOS transistor (MN3), and a node (N3) is connected to a terminal (P3) between the drains of PMOS and NMOS transistors (MP1, MN1). A reference capacitance (Cref) is formed at the node (N3) as a dummy capacitance. Currents (Ir, It) supplied from a power source to the nodes (N3, N1) are measured with current meters (61, 62), respectively and a current (Im) induced from the node (N2) and flowing to a ground level is measured with a current meter (63).

摘要翻译： CBCM电路能够单独测量测量目标电容的每个分量。 节点（N 1）电连接到PMOS和NMOS晶体管（MP 2，MN 2）的漏极之间的端子（P 2）。 作为目标电容形成部，在节点（N 1）和节点（N 2）之间形成耦合电容（C SUB）。 节点（N 2）经由端子（P 2）和NMOS晶体管（MN 3）连接到焊盘（58），并且节点（N 3）连接到端子（N 3）之间的端子（P 3） PMOS和NMOS晶体管（MP 1，MN 1）。 在节点（N 3）处形成参考电容（C SUB）作为虚拟电容。 分别用电流计（61,62）从电源向节点（N 3，N 1）提供的电流（I，R，I，T） 使用电流计（63）测量从节点（N 2）感应并流到地平面的电流（I SUB）。

公开(公告)号：US20060113533A1

公开(公告)日：2006-06-01

申请号：US11202210

申请日：2005-08-12

申请人： Yasuhiro Tamaki ,  Kyoji Yamashita ,  Katsuhiro Otani

发明人： Yasuhiro Tamaki ,  Kyoji Yamashita ,  Katsuhiro Otani

IPC分类号： H01L23/58

CPC分类号： H01L23/4824 ,  H01L27/0211 ,  H01L2924/0002 ,  H01L2924/00

摘要： In layout design of a semiconductor device including a device forming region formed on a substrate; an isolation region formed on the semiconductor substrate so as to surround the device forming region; a gate electrode formed on the device forming region; and a gate interconnect connected to the gate electrode and formed on both sides of the device forming region on the isolation region, the semiconductor device is designed as follows: The gate interconnect has a first portion with a larger dimension along the gate length direction than the gate electrode on one side of the device forming region and has a second portion with a larger dimension along the gate length direction than the gate electrode on the other side of the device forming region; and a distance between the first portion and the device forming region is equal to a distance between the second portion and the device forming region.

摘要翻译： 在包括在基板上形成的器件形成区域的半导体器件的布局设计中; 形成在所述半导体衬底上以围绕所述器件形成区域的隔离区; 形成在器件形成区域上的栅电极; 以及栅极互连，其连接到所述栅电极并形成在所述隔离区域上的器件形成区域的两侧，所述半导体器件被设计如下：所述栅极互连具有沿栅极长度方向具有比所述栅极长度方向更大的尺寸的第一部分 栅极电极在器件形成区域的一侧上，并且沿着栅极长度方向具有比器件形成区域的另一侧上的栅电极更大的尺寸的第二部分; 并且第一部分和器件形成区域之间的距离等于第二部分和器件形成区域之间的距离。

公开(公告)号：US20050093089A1

公开(公告)日：2005-05-05

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

公开(公告)号：US6124160A

公开(公告)日：2000-09-26

申请号：US192536

申请日：1998-11-17

申请人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

发明人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

IPC分类号： H01L29/43 ,  H01L21/02 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8242

CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S438/957

摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.

摘要翻译： MOS晶体管包括栅极氧化膜和通过第一和第二导体膜的叠层形成的栅电极。 电容元件包括由第一导体膜形成的下部电容电极，由与栅极氧化膜不同的绝缘膜制成的电容膜，由电容膜上的第二导体膜形成的上部电容电极，以及引线 电极由第二导电膜形成。 以与使用栅极氧化膜作为电容膜的情况相同的步骤，可以制造具有设置的电容膜的半导体器件，电容膜由与氮化物膜不同的氮化物膜等构成 栅氧化膜。 因此，使用具有每单位面积的大的电容值的电容膜，从而可以减小占用面积并且可以控制制造成本的增加。 在其中提供晶体管，电容元件，电阻膜等的半导体器件中，可以减小占用面积并且可以减少制造成本。

公开(公告)号：US5100234A

公开(公告)日：1992-03-31

申请号：US538186

申请日：1990-06-13

申请人： Yoriyuki Ishibashi ,  Ryoichi Hirano ,  Kyoji Yamashita

发明人： Yoriyuki Ishibashi ,  Ryoichi Hirano ,  Kyoji Yamashita

IPC分类号： G03F9/00

CPC分类号： G03F9/7049 ,  G03F9/7023

摘要： A first diffraction grating is formed on a mask, and a second diffraction grating is formed on a wafer. Two light beams having slightly different frequencies interfere with each other and are diffracted as they travel through the first diffraction grating, are reflected by the second diffraction grating, and again pass through the first diffraction grating. As a result, they change into thrice diffracted light beams. The diffracted light beams are combined into a detection light beam which has a phase shift .phi..sub.A representing the displacement between the wafer and the mask, or a phase shift .phi..sub.G representing the gap between the wafer and the mask. The detection light beam is converted into a detection signal. The phase difference between the detection signal and a reference signal having no phase shifts are calculated, thus determining phase shift .phi..sub.A or .phi..sub.G. The displacement or the gap is determined from the phase shift. In accordance with the displacement or the gap, the wafer and the mask are aligned to each other, or the gap between them is adjusted to a desired value. Since the detection signal is generated from diffracted light beams, its S/N ratio is sufficiently great. Therefore, the displacement or the gap is determined with high precision. In addition, it is possible with the invention to perform the aligning of the wafer and the mask and the adjusting of the gap therebetween, simultaneously. Further, the incident light may be either circularly polarized light or non-polarized light.

公开(公告)号：US07809181B2

公开(公告)日：2010-10-05

申请号：US11692352

申请日：2007-03-28

申请人： Kyoji Yamashita

发明人： Kyoji Yamashita

IPC分类号： G06K9/00 ,  G06K9/62 ,  G06K9/32

CPC分类号： G06K9/32 ,  G06T7/001 ,  G06T2207/30148

摘要： A pattern inspection apparatus includes a first unit configured to acquire an optical image of pattern, a second unit configured to generate a reference image to be compared, a third unit configured to calculate elements of a normal matrix for a least-squares method for calculating a displacement amount displaced from a preliminary alignment position, a forth unit configured to estimate a type of the reference image pattern, by using some of the elements of the normal matrix, a fifth unit configured to calculate the displacement amount based on the least-squares method, by using a normal matrix obtained by deleting predetermined elements depending upon the type of the pattern, a sixth unit configured to correct an alignment position between the optical image and the reference image to a position displaced by the displacement amount, and a seventh unit configured to compare the optical image and the reference image.

摘要翻译： 图案检查装置包括：被配置为获取图案的光学图像的第一单元，被配置为生成要比较的参考图像的第二单元;第三单元，被配置为计算最小二乘法的正态矩阵的元素， 位移量从初步对准位置移位，第四单元，被配置为通过使用正常矩阵的一些元素来估计参考图像图案的类型;第五单元，被配置为基于最小二乘法来计算位移量 通过使用通过根据图案的类型删除预定元素而获得的正常矩阵，第六单元，被配置为将光学图像与参考图像之间的对准位置校正到偏移位移量的位置，以及第七单元配置 以比较光学图像和参考图像。