公开(公告)号：US20050077955A1

公开(公告)日：2005-04-14

申请号：US10500875

申请日：2003-05-22

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

IPC分类号： H03H11/12 ,  H03H11/04 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03B1/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

公开(公告)号：US5751142A

公开(公告)日：1998-05-12

申请号：US795906

申请日：1997-03-04

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Masakatsu Maruyama ,  Masatoshi Matsushita ,  Koji Mochizuki

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Masakatsu Maruyama ,  Masatoshi Matsushita ,  Koji Mochizuki

IPC分类号： G05F3/24 ,  G05F3/26 ,  G05F3/20

CPC分类号： G05F3/247 ,  G05F3/262 ,  Y10S323/901

摘要： A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized. In this state, the diode element is cut off so that the offset voltage Voff is caused to disappear.

摘要翻译： 第一和第二参考电压产生电路的参考电压输出端通过二极管元件连接到运算放大器的电流镜电路的第一电流输入端。 在启动时，在基准电压输出端子上产生的基准电压为0V。因​​此，电流流向二极管元件，并在运算放大器上产生偏移电压Voff，使得产生故障点 消失。 因此，在存在具有预期值的基准电压的正常工作点和存在具有小于预期值的参考电压使运行稳定的故障点的情况下，产生的基准电压 在启动时升高，通过故障点达到正常工作点的预期电压值并稳定。 在这种状态下，二极管元件被切断，使偏移电压Voff消失。

公开(公告)号：US20080068101A1

公开(公告)日：2008-03-20

申请号：US11884270

申请日：2006-05-25

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

摘要翻译： 耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中mxn个相位耦合电路（30） 一定的相位模式相互连接形成一个环路。 逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

公开(公告)号：US07030688B2

公开(公告)日：2006-04-18

申请号：US10500875

申请日：2003-05-22

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

IPC分类号： H03K5/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

公开(公告)号：US06424184B1

公开(公告)日：2002-07-23

申请号：US09269315

申请日：1999-03-24

申请人： Akira Yamamoto ,  Shiro Sakiyama ,  Hiroyuki Nakahira ,  Masaru Fukuda ,  Akira Matsuzawa ,  Shiro Dosho ,  Shinichi Yamamoto

发明人： Akira Yamamoto ,  Shiro Sakiyama ,  Hiroyuki Nakahira ,  Masaru Fukuda ,  Akira Matsuzawa ,  Shiro Dosho ,  Shinichi Yamamoto

IPC分类号： H03D300

CPC分类号： G01R23/06 ,  G06F1/3203 ,  Y02D10/126

摘要： A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.

摘要翻译： 频率电压转换电路21接收时钟CLK作为输入，并根据时钟的频率提供电压IVdd作为输出。 频率电压转换电路21的输入和输出特性被调节以基本匹配给定的输入和输出特性。

公开(公告)号：US5699064A

公开(公告)日：1997-12-16

申请号：US509665

申请日：1995-07-31

申请人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  George Hayashi ,  Seizo Inagaki ,  Akira Matsuzawa

发明人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  George Hayashi ,  Seizo Inagaki ,  Akira Matsuzawa

IPC分类号： H03M3/04 ,  H03M1/78

CPC分类号： H03M3/376 ,  H03M3/50

摘要： In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).

摘要翻译： 在内插调制器中，使用从1比特量化器的一个时钟仅变化+/- 1的信号作为移位方向控制信号。 移位方向控制信号被提供给双向移位寄存器。 双向移位寄存器基于接收到的移位方向控制信号的值来移位数据。 来自双向移位寄存器的输出作为电阻梯型D / A转换器的控制信号给出。 电阻梯型D / A转换器输出与由上述控制信号选择的开关相对应的模拟电位。 因此，如果任意两位之间发生延迟差，则两个相邻的开关被简单地同时选择，使得电阻梯型D / A转换器的输出连续变化。 因此，可以提供具有高精度和增加的产量的电梯梯型的过采样D / A转换器，其没有毛刺（瞬时产生的噪声）。

公开(公告)号：US20100271142A1

公开(公告)日：2010-10-28

申请号：US12831715

申请日：2010-07-07

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

摘要翻译： 耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30） 点在某一相位模式下，相互连接形成一个回路。 逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

公开(公告)号：US07777580B2

公开(公告)日：2010-08-17

申请号：US11884270

申请日：2006-05-25

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

摘要翻译： 耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30） 点在某一相位模式下，相互连接形成一个回路。 逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

公开(公告)号：US5550544A

公开(公告)日：1996-08-27

申请号：US200493

申请日：1994-02-23

申请人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  Hiroyuki Nakahira ,  Toshiyuki Shono ,  Akira Matsuzawa

发明人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  Hiroyuki Nakahira ,  Toshiyuki Shono ,  Akira Matsuzawa

IPC分类号： H03M3/00 ,  H03M1/00

CPC分类号： H03M3/424 ,  H03M3/456

摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.

摘要翻译： 本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度 进入量化器并且其输出信号很小。 因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。

公开(公告)号：US20070096961A1

公开(公告)日：2007-05-03

申请号：US10580842

申请日：2004-10-14

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Shiro Dosho

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Shiro Dosho

IPC分类号： H03M7/30

CPC分类号： G10L21/04

摘要： In a signal processing device which performs data compression, a thinning circuit 1 generates thinned data by thinning input PCM data. For example, when a sampling rate fs of the PCM data (original data) is fs=10 Hz, thinned data of fs=1 Hz is generated. The determination circuit 2 controls the selection circuit 4 so that, based on the following expression: TOTAL1=|X(n)−X(n−1)|+|X(n−1)−X(n−2)|+ . . . +|X(n−8)−X(n−9)| if TOTAL1>C1, the input PCM data is selected, and if otherwise the thinned data is selected. The selected data and the determination result information of the determination circuit 2 are written into a memory 3. Therefore, data compression is performed with respect to original data with a simple circuit configuration and without losing required information of the original data.

摘要翻译： 在执行数据压缩的信号处理装置中，细化电路1通过稀释输入PCM数据来生成稀疏数据。 例如，当PCM数据（原始数据）的采样率fs为fs = 10Hz时，产生fs = 1Hz的稀疏数据。 确定电路2控制选择电路4，使得基于以下表达式：<？in-line-formula description =“In-line formula”end =“lead”？> TOTAL1 = | X（n）-X（ n-1）| + | X（n-1）-X（n-2）| +。 。 。 + | X（n-8）-X（n-9）| <？in-line-formula description =“内联公式”end =“tail”？>如果TOTAL 1> C 1，输入的PCM数据 选择，如果否则选择了稀疏数据。 所选择的数据和确定电路2的确定结果信息被写入存储器3。 因此，利用简单的电路配置对原始数据执行数据压缩，并且不丢失原始数据的所需信息。