公开(公告)号：US06165891A

公开(公告)日：2000-12-26

申请号：US435434

申请日：1999-11-22

申请人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

IPC分类号： H01L21/311 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  G03C5/00 ,  H01L21/302 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/31122 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.

摘要翻译： 通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。 该方法开始于提供其上具有第一导电层的半导体结构。 在第一导电层上形成钝化层。 第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。 第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。 图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。 碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。 可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。 硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。

公开(公告)号：US06436824B1

公开(公告)日：2002-08-20

申请号：US09346526

申请日：1999-07-02

申请人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

发明人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

IPC分类号： H01L2144

CPC分类号： H01L21/02211 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/3125 ,  H01L21/314 ,  H01L21/76807

摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

摘要翻译： 提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。 通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。 此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。 通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。 或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。 此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。

公开(公告)号：US06352921B1

公开(公告)日：2002-03-05

申请号：US09619377

申请日：2000-07-19

申请人： Licheng M. Han ,  Yi Xu ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

发明人： Licheng M. Han ,  Yi Xu ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

公开(公告)号：US06331479B1

公开(公告)日：2001-12-18

申请号：US09398294

申请日：1999-09-20

申请人： Jianxun Li ,  Mei Sheng Zhou ,  Yi Xu ,  Simon Chooi

发明人： Jianxun Li ,  Mei Sheng Zhou ,  Yi Xu ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76835

摘要： A method of fabricating trenches has been achieved. The method may be applied to damascene and dual damascene contacts to prevent damage to organic low dielectric constant materials due to photoresist ashing. A semiconductor substrate is provided. A first dielectric layer is deposited overlying the semiconductor substrate. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. An optional anti-reflective coating is applied. A photoresist layer is deposited. The photoresist layer is patterned to define openings for planned trenches. The second etch stopping layer is etched through to form a hard mask for the planned trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals. The first etch stopping layer is etched through to complete the trenches, and the integrated circuit device is completed.

摘要翻译： 已经实现了制造沟槽的方法。 该方法可以应用于镶嵌和双镶嵌接触，以防止由于光致抗蚀剂灰化而损坏有机低介电常数材料。 提供半导体衬底。 沉积在半导体衬底上的第一介电层。 第一蚀刻停止层沉积在第一介电层上。 第二蚀刻停止层沉积在第一蚀刻停止层上。 应用可选的抗反射涂层。 沉积光致抗蚀剂层。 图案化光致抗蚀剂层以限定计划沟槽的开口。 蚀刻第二蚀刻停止层以形成用于所计划的沟槽的硬掩模。 光致抗蚀剂层通过灰化被剥离，其中第一蚀刻停止层保护第一介电层免受由于氧自由基的存在的损害。 蚀刻第一蚀刻停止层以完成沟槽，并且完成集成电路器件。

公开(公告)号：US06690091B1

公开(公告)日：2004-02-10

申请号：US09666316

申请日：2000-09-21

申请人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

IPC分类号： H01L2348

CPC分类号： H01L21/76835 ,  H01L21/31122 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and the cap layers comprise low dielectric constant materials carbon nitride, boron nitride, or boron carbon nitride. The stack is patterned to form a via opening to the first conductive layer. A trench opening is formed stopping on the etch stop layer. A barrier layer of TaN, WN, TaSiN or Ta and a second conductive material is applied to the openings. Passivation, etch stop, or cap layers can be formed with carbon nitride by magnetron sputtering from a graphite target in a nitrogen atmosphere; boron carbon nitride by magnetron sputtering from a graphite target in a nitrogen and B2H6 atmosphere; or boron nitride by PECVD using B2H6, ammonia, and nitrogen.

摘要翻译： 具有减小的电容电介质堆叠的镶嵌结构包括在半导体上形成的第一导电层上的钝化，第一电介质，蚀刻停止层，第二介电层和覆盖层。 钝化，蚀刻停止和盖层包括低介电常数材料碳氮化物，氮化硼或氮碳化硼。 图案化堆叠以形成到第一导电层的通孔。 形成停止在蚀刻停止层上的沟槽开口。 将TaN，WN，TaSiN或Ta和第二导电材料的阻挡层施加到开口。 钝化，蚀刻停止或盖层可以通过在氮气气氛中的石墨靶磁控溅射由碳氮化物形成; 硼氮化物通过磁控溅射从石墨靶在氮气和B2H6气氛中; 或使用B2H6，氨和氮的PECVD的氮化硼。

公开(公告)号：US06348407B1

公开(公告)日：2002-02-19

申请号：US09805955

申请日：2001-03-15

申请人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76826 ,  H01L21/31058 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829

摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及在双镶嵌互连中使用改进低介电常数有机材料之间的粘附性的交替蚀刻停止。 此外，蚀刻停止材料是含硅材料，并被转变成低介电常数材料（k = 3.5至5），其在UV辐射和甲硅烷基化之后变成富氧氧化硅，氧等离子体。

公开(公告)号：US06265321B1

公开(公告)日：2001-07-24

申请号：US09550264

申请日：2000-04-17

申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Yi Xu

发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Yi Xu

IPC分类号： H01L2100

CPC分类号： H01L21/7682 ,  H01L21/76807

摘要： A method for reducing RC delay in integrated circuits by lowering the dielectric constant of the intermetal dielectric material between metal interconnects or metal damascene interconnects is described. The dielectric constant of the intermetal dielectric is lowered by introducing air into the intermetal dielectric between metal interconnections. An air bridge comprising a porous material, preferably amorphous silicon, porous silicon oxide, or porous silsesquioxane, is deposited over a layer containing a reactive organic material. An oxygen plasma treatment or an anisotropic etching through the pores in the air bridge layer removes at least a portion of the reactive material, leaving air plugs within the intermetal dielectric.

摘要翻译： 描述了通过降低金属互连或金属镶嵌互连之间的金属间电介质材料的介电常数来减小集成电路中的RC延迟的方法。 通过在金属互连之间的金属间电介质中引入空气来降低金属间电介质的介电常数。 包括多孔材料，优选非晶硅，多孔氧化硅或多孔倍半硅氧烷的空气桥被沉积在含有反应性有机材料的层上。 通过空气桥接层中的孔的氧等离子体处理或各向异性蚀刻去除至少一部分反应性材料，从而将空气塞留在金属间电介质内。

公开(公告)号：US20050090037A1

公开(公告)日：2005-04-28

申请号：US10978198

申请日：2004-10-29

申请人： Yakub Aliyu ,  Simon Chooi ,  Mei Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy

发明人： Yakub Aliyu ,  Simon Chooi ,  Mei Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/485 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

公开(公告)号：US06565664B2

公开(公告)日：2003-05-20

申请号：US10131519

申请日：2002-04-24

申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

IPC分类号： C23G114

CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

公开(公告)号：US06524910B1

公开(公告)日：2003-02-25

申请号：US09670329

申请日：2000-09-27

申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。