公开(公告)号：US06529029B1

公开(公告)日：2003-03-04

申请号：US09409973

申请日：1999-09-30

申请人： Michael R. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

发明人： Michael R. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

IPC分类号： G01R3128

CPC分类号： G01R31/303

摘要： A method for detecting substrate damage in a flip chip die, having a back side and a circuit side, that uses magnetic resonance imaging. The back side of the die is first globally thinned down and a region for examination is selected. A magnetic field is applied to the selected region and then the region is scanned with a magnetic resonance imaging arrangement. A plurality of perturbations are measured to generate an array of perturbation signals, which are then converted to a local susceptibility map of the selected region of the die. The susceptibility map of the selected region is then examined to determine if there is any substrate damage.

摘要翻译： 一种用于检测使用磁共振成像的具有背面和电路侧的倒装芯片的基板损伤的方法。 首先将模具的背面全局变薄，并选择检查区域。 将磁场施加到所选择的区域，然后用磁共振成像装置扫描该区域。 测量多个扰动以产生扰动信号阵列，然后将它们转换成所选择的模具区域的局部磁敏度图。 然后检查所选区域的磁敏度图，以确定是否存在任何底物损伤。

公开(公告)号：US06500699B1

公开(公告)日：2002-12-31

申请号：US09613667

申请日：2000-07-11

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

IPC分类号： H01L2150

CPC分类号： G01R31/2831 ,  G01R31/2853 ,  G01R31/2886 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： According to one aspect of the disclosure, the present invention provides methods and arrangements for testing a flip chip SOI semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For some chips, thinning removes substrate material useful for drawing heat away from the internal circuitry when the circuitry is running at high speeds. To compensate for this material loss, a special test fixture having a passive, corrosion-resistant heat-dissipating device is arranged to draw heat from the device.

摘要翻译： 根据本公开的一个方面，本发明提供了在芯片的背面已经变薄以暴露衬底中的选定区域之后测试倒装芯片SOI半导体器件的方法和布置。 对于某些芯片，当电路以高速运行时，薄化可去除用于从内部电路吸走热量的衬底材料。 为了补偿这种材料损失，设置了具有被动耐腐蚀的散热装置的特殊测试夹具来从装置抽取热量。

公开(公告)号：US06472760B1

公开(公告)日：2002-10-29

申请号：US09755011

申请日：2001-01-05

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

IPC分类号： H01L2348

CPC分类号： H01L23/525 ,  H01L21/76894 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

摘要： The present invention is directed to enhancing the analysis and modification of a flip chip integrated circuit die having silicon on insulator (SOI) structure. According to one example embodiment, an optical nanomachining arrangement is adapted to direct an optical beam, such as a laser, at a selected portion of the flip chip SOI structure. The optical beam performs device edits to modify the circuitry contained in the SOI selected portion without necessarily damaging surrounding circuitry. The ability to make such device edits is advantageous for various applications, such as in dies of complex, circuitry containing multiple stacked layers of components, and for dies having densely packed circuitry.

摘要翻译： 本发明旨在增强具有绝缘体上硅（SOI）结构的倒装芯片集成电路芯片的分析和修改。 根据一个示例性实施例，光学纳米加工布置适于在倒装芯片SOI结构的选定部分处引导诸如激光器的光束。 光束执行器件编辑以修改包含在SOI选择部分中的电路，而不必损坏周围电路。 进行这种设备编辑的能力对于各种应用是有利的，例如在复杂的管芯，包含多个堆叠层的层的电路中，以及具有密集封装的电路的管芯。

公开(公告)号：US06403388B1

公开(公告)日：2002-06-11

申请号：US09755005

申请日：2001-01-05

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

IPC分类号： H01L2166

CPC分类号： G01R31/316 ,  G01R31/311 ,  Y10S438/967 ,  Y10S438/977

摘要： A system and method provides for effective analysis of an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, the system includes a system (e.g., a nanomachining arrangement) adapted to remove a selected portion of the backside of a semiconductor device having SOI structure, and to electrically isolate a selected portion of circuitry on the SOI semiconductor device circuitry side. The isolated circuitry then is analyzed.

摘要翻译： 一种系统和方法提供了对具有绝缘体上硅（SOI）结构的集成电路的有效分析。 根据本发明的一个示例性实施例，该系统包括适于去除具有SOI结构的半导体器件的背面的选定部分的系统（例如，纳米加工布置），并且将所选择的电路部分电隔离 SOI半导体器件电路侧。 然后分析隔离电路。

公开(公告)号：US06372529B1

公开(公告)日：2002-04-16

申请号：US09408616

申请日：1999-09-30

申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

IPC分类号： G01R3126

CPC分类号： G01R31/31905 ,  G01R3/00 ,  G01R31/2884

摘要： Access to portions of semiconductor devices is enhanced via a method and system for probing between circuitry in the semiconductor device during post-manufacture analysis of the semiconductor device. According to an example embodiment of the present invention, an elongated conductive via probe is formed in a semiconductor device having circuitry in a circuit side opposite a back side. The probe is formed by first removing substrate from the semiconductor device and forming an exposed region over a target node between circuitry in the device. A narrow conductor is then formed for accessing the target node, with the conductor and extending between the circuitry and into the back side and forming the elongated conductive via probe. The probe is accessed and used for analyzing the device. In this manner, access to a difficult-to-reach target node, such as a node between closely-placed transistors, is facilitated.

摘要翻译： 通过用于在半导体器件的后制造分析期间在半导体器件中的电路之间探测的方法和系统来增强对半导体器件的部分的访问。 根据本发明的示例性实施例，在具有在背侧相反的电路侧中的电路的半导体器件中形成细长的导电通孔探针。 通过首先从半导体器件去除衬底并在器件中的电路之间的目标节点上形成暴露区域来形成探针。 然后形成窄导体，用于与导体接合目标节点，并在电路之间延伸并进入后侧，并形成细长的导电通孔探针。 探头被访问并用于分析设备。 以这种方式，便于访问难以达到的目标节点，诸如紧密放置的晶体管之间的节点。

公开(公告)号：US06352871B1

公开(公告)日：2002-03-05

申请号：US09409089

申请日：1999-09-30

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Glen Gilfeather

IPC分类号： H01L2166

CPC分类号： G01R31/312 ,  G01R31/2884 ,  G01R31/303

摘要： The ability to excite virtually any portion of semiconductor device is enhanced via a grid formed for exciting circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for exciting various target circuitry within the device by exciting the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

摘要翻译： 实际上激发半导体器件的任何部分的能力通过为半导体器件中的激励电路形成的电网来增强。 根据本发明的一个示例性实施例，在半导体器件中形成有延伸超过目标电路的具有多个窄探针点的格栅。 电网被访问并用于通过激励对应于期望访问的目标电路的部分的电网部分来激发装置内的各种目标电路。

公开(公告)号：US06281025B1

公开(公告)日：2001-08-28

申请号：US09409320

申请日：1999-09-30

申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

IPC分类号： H01L2100

CPC分类号： H01L22/26 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311

摘要： Substrate removal for post-manufacturing analysis of a semiconductor device is enhanced via a method and system that utilizes ion beam etching, to etch the backside of a semiconductor chip, and utilizes SIMS as a detection technique to not only control removal of the substrate from the backside of the chip but also to determine the endpoint of the removal process. In an example embodiment there is described a method for removing substrate from the backside of a semiconductor chip as a function of detected concentration levels of a selected substrate material that is sputtered off of a region of the substrate.

摘要翻译： 通过利用离子束蚀刻，蚀刻半导体芯片的背面的方法和系统来增强对半导体器件的后制造分析的衬底去除，并且利用SIMS作为检测技术，不仅可以控制从衬底的去除 芯片的背面还可以确定去除过程的终点。 在一个示例性实施例中，描述了从半导体芯片的背面去除衬底的方法，其作为从衬底区域溅射的所选择的衬底材料的检测浓度水平的函数。

公开(公告)号：US06452176B1

公开(公告)日：2002-09-17

申请号：US09359103

申请日：1999-07-22

申请人： Brennan V. Davis

发明人： Brennan V. Davis

IPC分类号： H01J3730

CPC分类号： H01J37/2955

摘要： According to one aspect of the disclosure, a method for detecting a degree of substrate damage in an integrated circuit die is provided. In one example embodiment, the back side of the die is thinned and an examination region is exposed. An electron beam is used to scan the region, and backscattered electrons are detected in response. The detected backscattered electrons are used to provide an electron channeling pattern for the scanned region. The electron channeling pattern is then compared to a reference pattern and used to determine a degree of substrate damage.

摘要翻译： 根据本公开的一个方面，提供了一种用于检测集成电路管芯中的衬底损伤程度的方法。 在一个示例性实施例中，模具的背面变薄并且检查区域被暴露。 电子束用于扫描该区域，响应中检测到反向散射的电子。 使用检测的反向散射电子来为扫描区域提供电子通道图案。 然后将电子沟道图案与参考图案进行比较，并用于确定衬底损伤程度。

公开(公告)号：US06724928B1

公开(公告)日：2004-04-20

申请号：US09496532

申请日：2000-02-02

申请人： Brennan V. Davis

发明人： Brennan V. Davis

IPC分类号： G06K900

CPC分类号： G01R31/311

摘要： Post-manufacturing analysis of a semiconductor chip is enhanced via a method and system for viewing emissions through substrate in the back side of the chip. According to an example embodiment of the present invention, a portion of circuitry in a semiconductor chip is excited, and an emission is generated. An optical microscope is directed at the backside of the chip, and an image of the emission is obtained. The optical microscope is coupled to an indium-gallium-arsenic (InGaAs) camera that is used to detect the emission. In this manner, emissions can be detected through substrate in a semiconductor chip.

摘要翻译： 通过用于观察在芯片背面的衬底的发射的方法和系统来增强半导体芯片的制造后分析。 根据本发明的示例性实施例，半导体芯片中的电路的一部分被激发，并且产生发射。 光学显微镜指向芯片的背面，并获得发射的图像。 光学显微镜耦合到用于检测发射的铟镓砷（InGaAs）相机。 以这种方式，可以通过半导体芯片中的衬底检测发射。