METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN
    31.
    发明申请
    METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN 有权
    利用现场清洁优化硅酸盐污染物尺寸的方法

    公开(公告)号:US20090286389A1

    公开(公告)日:2009-11-19

    申请号:US12122840

    申请日:2008-05-19

    IPC分类号: H01L21/3205 H01L21/4763

    摘要: A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

    摘要翻译: 一种方法,包括在衬底上形成半导体器件的栅极,并且蚀刻栅极侧面上的侧壁间隔物以提供接近值,其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域,其中在连续真空中进行蚀刻和预清洁。

    Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors
    32.
    发明授权
    Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors 有权
    用于增强应力传递到NMOS和PMOS晶体管的沟道区域的技术

    公开(公告)号:US07344984B2

    公开(公告)日:2008-03-18

    申请号:US11468450

    申请日:2006-08-30

    IPC分类号: H01L21/44 H01L21/4763

    摘要: A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

    摘要翻译: 提供了一种方法和半导体器件,其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上,而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外,由于本发明构思,应变感应接触层可以直接形成在相应的大致L形间隔元件上,从而进一步增强应力传递机构。

    Methods of Forming Metal Silicide Regions on Semiconductor Devices
    33.
    发明申请
    Methods of Forming Metal Silicide Regions on Semiconductor Devices 有权
    在半导体器件上形成金属硅化物区域的方法

    公开(公告)号:US20130157450A1

    公开(公告)日:2013-06-20

    申请号:US13331842

    申请日:2011-12-20

    IPC分类号: H01L21/283

    摘要: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

    摘要翻译: 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中,该方法包括在半导体衬底之上形成牺牲栅极结构,在形成金属硅化物区域之后,执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域, 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构,所述替换栅极结构由至少一个金属层组成。

    Method of forming sidewall spacers
    39.
    发明授权
    Method of forming sidewall spacers 有权
    形成侧墙的方法

    公开(公告)号:US07316975B2

    公开(公告)日:2008-01-08

    申请号:US11177216

    申请日:2005-07-08

    IPC分类号: H01L21/302 H01L21/461

    CPC分类号: H01L21/823468

    摘要: A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

    摘要翻译: 提供了包括第一晶体管元件和第二晶体管元件的衬底。 一层材料沉积在第一晶体管元件和第二晶体管元件上。 材料层的一部分被修饰,其可以例如通过用离子照射部分或执行各向同性蚀刻工艺来实现,以减小其厚度。 执行适于比位于第二晶体管元件上方的层的未修改部分更快地去除材料层的修饰部分的蚀刻工艺。