公开(公告)号：US11757034B2

公开(公告)日：2023-09-12

申请号：US17731159

申请日：2022-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hung-Sen Wang ,  Yun-Ta Tsai ,  Ruey-Hsin Liu ,  Shih-Fen Huang ,  Ho-Chun Liou

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L27/0617 ,  H01L29/0653 ,  H01L29/42356 ,  H01L29/66681

Abstract: A high-voltage device includes a first frame-like isolation and a second frame-like isolation separated from each other, a first frame-like gate structure covering the first frame-like isolation, a second frame-like gate structure covering the second frame-like isolation, a first drain region enclosed by the first frame-like isolation, a second drain region enclosed by the second frame-like isolation, a first frame-like source region surrounding the first frame-like gate structure, a second frame-like source region surrounding the second frame-like gate structure, a first doped region surrounding the first and second frame-like gate structures, and a second doped region disposed between the first and second frame-like gate structures. The first and second drain regions, and the first and second frame-like source regions include a first conductivity type. The first and the second doped region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

公开(公告)号：US20220367564A1

公开(公告)日：2022-11-17

申请号：US17874446

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yuan Shih ,  Shih-Fen Huang ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H01L27/20 ,  H01L41/314 ,  H01L41/09

Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

公开(公告)号：US10164005B2

公开(公告)日：2018-12-25

申请号：US15072906

申请日：2016-03-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Felix Ying-Kit Tsui ,  Shih-Fen Huang

IPC: H01L29/00 ,  H01L49/02

Abstract: The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes are insulated with one another. The semiconductor structure further includes a plug in the capacitor and surrounded by the plurality of electrodes.

公开(公告)号：US20170067890A1

公开(公告)日：2017-03-09

申请号：US15356503

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Yi-Hsien Chang ,  Shih-Fen Huang

IPC: G01N33/543 ,  G01N27/414

CPC classification number: G01N33/54373 ,  G01N27/4145 ,  G01N27/4148 ,  H01L51/0093 ,  H01L51/0512

Abstract: Dual-gate ion-sensitive field effect transistor (ISFET) and methods implementing the dual-gate ISFETs for disease diagnostics are disclosed herein. An exemplary method includes providing a biological sample to a dual-gate ISFET. The dual-gate ISFET includes a fluidic gate structure and a gate structure, where the fluidic gate structure and the gate structure are disposed over opposite surfaces of a device substrate. The method further includes generating enzymatic reactions from enzyme-modified detection mechanisms. The enzyme-modified detection mechanisms release ions into an electrolyte solution of the fluidic gate structure. The method further includes biasing the fluidic gate structure and the gate structure to generate an electrical signal as a sensing layer of the fluidic gate structure reacts with the ions. The electrical signal indicates an ion concentration in the electrolyte solution that correlates with a presence or a quantity of target analytes in the biological sample.

Abstract translation: 本文公开了双栅离子敏感场效应晶体管（ISFET）和实现用于疾病诊断的双栅极ISFET的方法。 一种示例性方法包括向双栅极ISFET提供生物样品。 双栅极ISFET包括流体栅极结构和栅极结构，其中流体栅极结构和栅极结构设置在器件衬底的相对表面上。 该方法还包括从酶修饰的检测机制产生酶反应。 酶修饰的检测机制将离子释放到流体门结构的电解质溶液中。 该方法还包括偏压流体栅极结构和栅极结构以在流体栅极结构的感测层与离子反应时产生电信号。 电信号表示与生物样品中目标分析物的存在或数量相关的电解质溶液中的离子浓度。

公开(公告)号：US12227410B2

公开(公告)日：2025-02-18

申请号：US18404922

申请日：2024-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Po Chen Yeh ,  Yi-Hsien Chang ,  Fu-Chun Huang ,  Ching-Hui Lin ,  Chiahung Liu ,  Shih-Fen Huang ,  Chun-Ren Cheng

IPC: B81B7/00 ,  B81C1/00

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

公开(公告)号：US20250048660A1

公开(公告)日：2025-02-06

申请号：US18921057

申请日：2024-10-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yan-Jie Liao

IPC: H01G4/30

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure that includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a first electrode and a second electrode stacked over the substrate. A dielectric layer is arranged between the first electrode and the second electrode. A getter layer is disposed over the substrate and is separated from the dielectric layer by the first electrode. The MIM device includes a middle portion having a first non-zero concentration of hydrogen and a peripheral portion having both a second non-zero concentration of hydrogen that is greater than the first non-zero concentration and a third non-zero concentration of hydrogen that is less than the first non-zero concentration. The middle portion includes the dielectric layer and the peripheral portion includes the getter layer.

公开(公告)号：US20240373753A1

公开(公告)日：2024-11-07

申请号：US18772399

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Alexander Kalnitsky ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H10N30/00 ,  G01N25/58 ,  H10N30/04 ,  H10N30/067 ,  H10N30/87 ,  H10N30/063

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

公开(公告)号：US20240324463A1

公开(公告)日：2024-09-26

申请号：US18679537

申请日：2024-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

IPC: H10N30/30 ,  G01N27/414 ,  H10N30/05 ,  H10N30/08 ,  H10N30/87 ,  H10N30/88

CPC classification number: H10N30/302 ,  G01N27/4141 ,  H10N30/05 ,  H10N30/08 ,  H10N30/878 ,  H10N30/88

Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.

公开(公告)号：US11923429B2

公开(公告)日：2024-03-05

申请号：US17405307

申请日：2021-08-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/4238 ,  H01L21/26513 ,  H01L21/28123 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/78 ,  H01L29/4916

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US20230378251A1

公开(公告)日：2023-11-23

申请号：US18362146

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H10N69/00 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/764 ,  H01L29/94 ,  H01L23/00

CPC classification number: H01L28/91 ,  H01L21/32139 ,  H01L28/92 ,  H01L21/02164 ,  H01L29/66181 ,  H01L21/764 ,  H01L29/945 ,  H01L23/562 ,  H01L21/02236

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.