公开(公告)号：US12148717B2

公开(公告)日：2024-11-19

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US11710764B2

公开(公告)日：2023-07-25

申请号：US16020131

申请日：2018-06-27

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Sagnik Dey ,  Luigi Colombo ,  Haowen Bu ,  Scott Robert Summerfelt ,  Mark Robert Visokay ,  John Paul Campbell

IPC: H01L21/285 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L28/91 ,  H01L21/28518 ,  H01L21/306 ,  H01L21/32133

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

公开(公告)号：US20230059848A1

公开(公告)日：2023-02-23

申请号：US17828356

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott Robert Summerfelt ,  Benjamin Stassen Cook ,  Simon Joshua Jacobs ,  Stefan Herzer

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768

Abstract: A device includes a die with a metallization stack. The device includes a substrate with a first region, a second region and a third region that underly the metallization stack and a first isolation trench filled with a polymer dielectric that extends between the first region and the second region of the substrate. The device also includes a second isolation trench filled with the polymer dielectric that extends between the second region and the third region. The polymer dielectric overlays a periphery of the substrate.

公开(公告)号：US11495607B2

公开(公告)日：2022-11-08

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US20210354977A1

公开(公告)日：2021-11-18

申请号：US17320188

申请日：2021-05-13

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Adam Joseph Fruehling ,  Kelly Jay Taylor

IPC: B81B3/00

Abstract: In described examples, a microelectromechanical system (MEMS) is located on a substrate. A silicon nitride (SiN) layer on a portion of the substrate. A mechanical structure has first and second ends. The first end is embedded in the SiN layer, and the second end is cantilevered from the SiN layer.

公开(公告)号：US09070575B2

公开(公告)日：2015-06-30

申请号：US13953476

申请日：2013-07-29

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

IPC: H01L21/02 ,  H01L27/08 ,  H01L27/115 ,  H01L29/92 ,  H01L49/02 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

公开(公告)号：US20140147940A1

公开(公告)日：2014-05-29

申请号：US14088572

申请日：2013-11-25

Applicant: Texas Instruments Incorporated

Inventor： Mark Robert Visokay ,  Scott Robert Summerfelt

IPC: H01L49/02 ,  C23C2/00

CPC classification number: H01L21/2855 ,  B22F3/10 ,  B22F5/00 ,  C22C28/00 ,  C22C32/001 ,  C22C32/0015 ,  C22C32/0031 ,  C22C32/0042 ,  C23C14/08 ,  C23C14/082 ,  C23C14/3414 ,  H01L21/32133 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.

Abstract translation: 用于导电氧化物的溅射靶，例如SrRuO 3，用于在集成电路中与铁电材料接触的导电膜的溅射沉积。 溅射靶是通过将导电氧化物的粉末混合物与铁电体材料的组分之一的氧化物的烧结剂烧结而形成的。 作为铁电材料的钛酸锆酸铅（PZT）的例子，烧结剂是氧化铅，氧化锆，氧化钛中的一种以上。 所得到的溅射靶具有更高的密度和更低的孔隙率，导致改进的溅射沉积膜不包括超过与该膜相邻沉积的铁电材料的原子种类的原子种类。

公开(公告)号：US20130313679A1

公开(公告)日：2013-11-28

申请号：US13953476

申请日：2013-07-29

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

IPC: H01L27/08 ,  H01L27/06

CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。