公开(公告)号：US20230025885A1

公开(公告)日：2023-01-26

申请号：US17960383

申请日：2022-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US11467622B2

公开(公告)日：2022-10-11

申请号：US17182547

申请日：2021-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US20220269304A1

公开(公告)日：2022-08-25

申请号：US17182547

申请日：2021-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  G06F1/12 ,  H03K5/00

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US11132050B2

公开(公告)日：2021-09-28

申请号：US16451260

申请日：2019-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US10930328B2

公开(公告)日：2021-02-23

申请号：US16674525

申请日：2019-11-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G06F11/10 ,  G06F11/14 ,  G06F12/02 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/00 ,  G11C14/00

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

公开(公告)号：US10796738B2

公开(公告)日：2020-10-06

申请号：US15899302

申请日：2018-02-19

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/3562 ,  G06F11/10 ,  G11C14/00 ,  G11C7/22 ,  G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/00

Abstract: A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.

公开(公告)号：US20190162590A1

公开(公告)日：2019-05-30

申请号：US16191430

申请日：2018-11-14

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US09715911B2

公开(公告)日：2017-07-25

申请号：US13769963

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/00 ,  G11C7/22 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

公开(公告)号：US09520862B2

公开(公告)日：2016-12-13

申请号：US14447901

申请日：2014-07-31

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感复位预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，静止控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US09099998B2

公开(公告)日：2015-08-04

申请号：US13973274

申请日：2013-08-22

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/289 ,  H03K3/3562 ,  G11C11/419

CPC classification number: H03K3/35625 ,  G11C11/419

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。