公开(公告)号：US07525173B2

公开(公告)日：2009-04-28

申请号：US11485341

申请日：2006-07-13

申请人： Hyang-Ja Yang ,  Su-Jin Park ,  Uk-Rae Cho ,  Sung-Hoon Kim

发明人： Hyang-Ja Yang ,  Su-Jin Park ,  Uk-Rae Cho ,  Sung-Hoon Kim

IPC分类号： H01L29/78

CPC分类号： H01L27/0203 ,  H01L21/823418 ,  H01L21/823481

摘要： In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.

摘要翻译： 在多个金属氧化物半导体（MOS）晶体管的布局结构中，布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域 通过沟槽隔离，以及第二组MOS晶体管，其具有分配给组有源区的第二漏极区和第二源极区。 第二组布置在第一组与组有源区的边缘之间。 第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

公开(公告)号：US07454672B2

公开(公告)日：2008-11-18

申请号：US10748906

申请日：2003-12-30

申请人： Jong-Cheol Lee ,  Su-Chul Kim ,  Uk-Rae Cho

发明人： Jong-Cheol Lee ,  Su-Chul Kim ,  Uk-Rae Cho

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C2029/1804

摘要： Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.

摘要翻译： 提供了在合并的数据输入/输出引脚（DQ）测试模式中可以以单个数据速率（SDR）或双数据速率（DDR）模式进行测试的半导体存储器件。 该装置包括第一路径电路，第二路径电路和被配置为生成具有SDR和/或DDR模式的合并数据位的合并输出发生器。

公开(公告)号：US07016257B2

公开(公告)日：2006-03-21

申请号：US10790262

申请日：2004-03-01

申请人： Nam-Seog Kim ,  Uk-Rae Cho ,  Yong-Jin Yoon

发明人： Nam-Seog Kim ,  Uk-Rae Cho ,  Yong-Jin Yoon

IPC分类号： G11C8/00

CPC分类号： G11C29/12015 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C29/14

摘要： A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address input circuit; a data output circuit for outputting the data read out from the selected memory cell in response to first and second data clock signals; and an internal clock generating circuit for generating the address clock signal and the first and second data clock signals in response to an external clock signal and a complementary clock signal thereof, wherein the address clock signal and the first and second data clock signals have twice the frequency (or half the period) of the external clock signal when in a test mode.

摘要翻译： 一种半导体存储器件，包括：存储器单元阵列; 地址输入电路，用于响应于地址时钟信号接收外部地址; 选择电路，用于响应于从地址输入电路输出的地址来选择存储单元; 数据输出电路，用于响应于第一和第二数据时钟信号输出从所选存储单元读出的数据; 以及内部时钟发生电路，用于响应于外部时钟信号及其互补时钟信号产生地址时钟信号和第一和第二数据时钟信号，其中地址时钟信号和第一和第二数据时钟信号具有两倍 在测试模式时外部时钟信号的频率（或一半周期）。

公开(公告)号：US06901014B2

公开(公告)日：2005-05-31

申请号：US10445468

申请日：2003-05-27

申请人： Young-Jae Son ,  Uk-Rae Cho ,  Kwang-Jin Lee

发明人： Young-Jae Son ,  Uk-Rae Cho ,  Kwang-Jin Lee

IPC分类号： G01R31/28 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

CPC分类号： G11C29/12005 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

摘要： Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.

摘要翻译： 能够筛选半导体存储器件中的缺陷或弱存储器单元的电路和方法。 在一个方面，半导体存储器件包括用于SRAM单元的第一和第二驱动器。 第一驱动器连接在电源电压和电池之间，其响应于电池功率控制信号将电源电压提供给电池。 第二驱动器连接在电源信号和单元之间，其响应于单元断电信号而向电池提供低于电源电压的电压。 用于筛选有缺陷或弱电池的方法不需要时间来稳定电压变化之后的电路状况，以从常规测试器提供低于电源电压的电压，因为电池停电信号激活导致电源电压的驱动器 低于要直接加载到电池的电源电压，这样可以减少用于筛选有缺陷的电池的测试时间。

公开(公告)号：US06583647B2

公开(公告)日：2003-06-24

申请号：US10055206

申请日：2002-01-23

申请人： Nam-Seog Kim ,  Uk-Rae Cho ,  Kwang-Jin Lee

发明人： Nam-Seog Kim ,  Uk-Rae Cho ,  Kwang-Jin Lee

IPC分类号： H03K190175

CPC分类号： H03K3/356113 ,  H03K3/356165 ,  H03K5/06

摘要： A level converting apparatus for converting an original voltage level to a wanted voltage level is disclosed. The level converter includes a converting part for outputting a level-converting signal having a different level from that of an input signal in response to an input signal; a delay part for delaying the level-converted signal of the converting part by a predetermined time; and a self-reset part for generating a reset signal in response to the delayed level-converted signal of the delay part to output it to the converting part so that a pulse width of the level-converted signal as output is set as much as the sum of a predetermined delay time and an internal operation delay time.

摘要翻译： 公开了一种用于将原始电压电平转换成所需电压电平的电平转换装置。 电平转换器包括转换部分，用于响应于输入信号输出具有与输入信号不同的电平的电平转换信号; 用于将转换部分的电平转换信号延迟预定时间的延迟部分; 以及自复位部分，用于响应于延迟部分的延迟电平转换信号产生复位信号，以将其输出到转换部分，使得作为输出的电平转换信号的脉冲宽度设置为 预定延迟时间和内部操作延迟时间的和。

公开(公告)号：US4912055A

公开(公告)日：1990-03-27

申请号：US265420

申请日：1988-10-31

申请人： Sung-Ki Min ,  Chang-Won Kahng ,  Uk-Rae Cho ,  Jong-Mil Youn ,  Suk-Gi Choi

发明人： Sung-Ki Min ,  Chang-Won Kahng ,  Uk-Rae Cho ,  Jong-Mil Youn ,  Suk-Gi Choi

IPC分类号： H01L29/73 ,  C08G18/30 ,  C08G18/32 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/10 ,  H01L29/732

CPC分类号： H01L21/8249

摘要： A method for fabricating a BiCMOS device to achieve a maximum performance through a of minimum processing steps, in which the BiCMOS device is exemplary for its high integration and high performance MOS transistors, self-aligned metal contact emitter type bipolar transistors having high load driving force, high performance matching characteristics and high integration, and self-aligned polycrystalline silicon emitter type bipolar transistors having high integration and high speed characteristics in low current, thereby being used in high integration, high speed digital and precise analog system. The method includes a plurality of fabrication steps including ion-implantation, formation of a thin film oxide layer, deposition of a nitride layer, etching of the oxide layer, formation of windows and others, alternately and/or sequentially in a single chip substrate.

摘要翻译： 一种用于制造BiCMOS器件以通过最小处理步骤实现最大性能的方法，其中BiCMOS器件是其高集成度和高​​性能MOS晶体管的示例性，具有高负载驱动力的自对准金属接触发射极型双极晶体管 ，高性能匹配特性和高集成度，以及在低电流下具有高集成度和高​​速特性的自对准多晶硅发射极型双极晶体管，从而被用于高集成度，高速数字和精确模拟系统。 该方法包括在单个芯片衬底中交替地和/或顺序地包括离子注入，薄膜氧化物层的形成，氮化物层的沉积，氧化物层的蚀刻，窗口等的形成的多个制造步骤。

公开(公告)号：US08578227B2

公开(公告)日：2013-11-05

申请号：US12944787

申请日：2010-11-12

申请人： Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

发明人： Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G06F11/24

摘要： A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

摘要翻译： 用于片上系统的测试装置包括顺序逻辑电路和测试电路。 顺序逻辑电路通过根据串行时钟信号和串行使能信号将串行输入信号转换为并行格式产生测试输入信号，并通过将测试输出信号转换成串行格式来响应于 串行时钟信号和串行使能信号。 测试电路包括至少一个延迟单元，其与执行片上系统的原始功能的逻辑电路分离，响应于系统时钟信号，使用测试输入信号对至少一个延迟单元执行延迟测试 和测试使能信号，并将测试输出信号提供给顺序逻辑电路，其中测试输出信号表示延迟测试的结果。

公开(公告)号：US07616512B2

公开(公告)日：2009-11-10

申请号：US12347233

申请日：2008-12-31

申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

IPC分类号： G11C7/00

CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

公开(公告)号：US07154312B2

公开(公告)日：2006-12-26

申请号：US11031129

申请日：2005-01-07

申请人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

发明人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC分类号： H03L7/00

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/135

摘要： An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

摘要翻译： 提供了一种用于产生用于获取精确同步的内部时钟信号的装置。 该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列 镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列 以及产生内部时钟信号的输出缓冲器。 可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

公开(公告)号：US20060238227A1

公开(公告)日：2006-10-26

申请号：US11371555

申请日：2006-03-09

申请人： Nam-Seog Kim ,  Uk-Rae Cho

发明人： Nam-Seog Kim ,  Uk-Rae Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/07

摘要： A delay-locked loop (DLL) circuit and a method for generating transmission core clock signals are provided, where the DLL circuit receives an applied external clock signal and generates a transmission core clock signal, the DLL circuit includes a delay circuit unit and a transmission core clock signal generating unit, the delay circuit unit delays the external clock signal through a plurality of delay units configured in a chain type and outputs a plurality of reference clock signals having different phases, the transmission core clock signal generating unit independently selects and controls two reference signals from the plurality of reference clock signals and thus independently generates transmission core clock signals by the number corresponding to ½ times the number of reference clock signals, and the transmission core clock signals have different phases and a period equal to a period of the external clock signal, wherein transmission core clock signals having a precise phase difference are generated individually and independently.

摘要翻译： 提供延迟锁定环路（DLL）电路和用于产生传输核心时钟信号的方法，其中DLL电路接收所施加的外部时钟信号并产生传输核心时钟信号，该DLL电路包括延迟电路单元和传输 核心时钟信号发生单元，延迟电路单元通过链式配置的多个延迟单元延迟外部时钟信号，并输出具有不同相位的多个参考时钟信号，发送核心时钟信号发生单元独立地选择和控制两个 来自多个参考时钟信号的参考信号，从而独立地产生与参考时钟信号数量的1/2的数量的传输核心时钟信号，并且传输核心时钟信号具有不同的相位和周期等于外部的周期 时钟信号，其中具有精确相位di的传输核心时钟信号 单独和独立地产生参考。