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公开(公告)号:US20250006739A1
公开(公告)日:2025-01-02
申请号:US18345467
申请日:2023-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Ming Lin , Chun-I Wu , Tsung-Kai Chiu , Wei-Yen Woon , Szuya Liao
IPC: H01L27/092 , H01L21/822 , H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/775
Abstract: A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.
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公开(公告)号:US12034058B2
公开(公告)日:2024-07-09
申请号:US18129961
申请日:2023-04-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Cheng-Ming Lin , Sai-Hooi Yeong , Ziwei Fang , Chi On Chui , Huang-Lin Chao
CPC classification number: H01L29/516 , H01L21/02356 , H01L21/28176 , H01L27/0886 , H01L29/66795 , H01L29/6684 , H01L29/78391 , H01L29/785 , H01L29/7851
Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.
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公开(公告)号:US11621338B2
公开(公告)日:2023-04-04
申请号:US17228415
申请日:2021-04-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Cheng-Ming Lin , Sai-Hooi Yeong , Ziwei Fang , Chi On Chui , Huang-Lin Chao
Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.
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公开(公告)号:US20220350235A1
公开(公告)日:2022-11-03
申请号:US17809979
申请日:2022-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US11282940B2
公开(公告)日:2022-03-22
申请号:US16946736
申请日:2020-07-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Ming Lin , Kai Tak Lam , Sai-Hooi Yeong , Chi On Chui , Ziwei Fang
Abstract: A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca21 space group.
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公开(公告)号:US20220066312A1
公开(公告)日:2022-03-03
申请号:US17007920
申请日:2020-08-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号:US11195938B2
公开(公告)日:2021-12-07
申请号:US16526650
申请日:2019-07-30
Inventor: Cheng-Ming Lin , Sai-Hooi Yeong , Chi-On Chui , Ziwei Fang
IPC: G11C11/22 , H01L21/28 , H01L27/1159 , H01L29/78 , H01L21/283 , H01L21/3205 , H01L29/06 , H01L29/66 , H01L29/51 , H01L21/02 , H01L29/423
Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.
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公开(公告)号:US11139397B2
公开(公告)日:2021-10-05
申请号:US16572255
申请日:2019-09-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Ming Lin , Sai-Hooi Yeong , Ziwei Fang , Chi On Chui , Huang-Lin Chao
Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.
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公开(公告)号:US11031490B2
公开(公告)日:2021-06-08
申请号:US16454854
申请日:2019-06-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Ming Lin , Sai-Hooi Yeong , Chi On Chui , Ziwei Fang , Huang-Lin Chao
Abstract: A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.
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公开(公告)号:US11018256B2
公开(公告)日:2021-05-25
申请号:US16549245
申请日:2019-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Ming Lin , Sai-Hooi Yeong , Ziwei Fang , Chi On Chui , Huang-Lin Chao
Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.
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