公开(公告)号：US20210091229A1

公开(公告)日：2021-03-25

申请号：US16578389

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

公开(公告)号：US10741678B2

公开(公告)日：2020-08-11

申请号：US15798273

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Carlos H. Diaz ,  Chih-Sheng Chang ,  Cheng-Yi Peng ,  Ling-Yen Yeh ,  Chien-Hsing Lee

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L29/51 ,  H01L29/78

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

公开(公告)号：US10734472B2

公开(公告)日：2020-08-04

申请号：US16392158

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L49/02 ,  H01L27/1159 ,  H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L27/11585 ,  H01L29/51 ,  H01L29/66

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

公开(公告)号：US20190165103A1

公开(公告)日：2019-05-30

申请号：US15904699

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Tung-Ying Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/10 ,  H01L29/66 ,  H01L23/31 ,  H01L29/51 ,  H01L21/465 ,  H01L29/08 ,  H01L21/768 ,  H01L29/24 ,  H01L29/78 ,  H01L29/06 ,  H01L21/441

Abstract: A semiconductor device includes a fin structure, a channel layer and a gate stack. The channel layer is disposed on sidewalls of the fin structure, wherein the channel layer contains a two-dimensional (2D) material. The gate stack is disposed over the channel layer, wherein the gate stack includes a ferroelectric layer.

公开(公告)号：US20190131382A1

公开(公告)日：2019-05-02

申请号：US15795610

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L49/02 ,  H01L21/02

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

公开(公告)号：US12302636B2

公开(公告)日：2025-05-13

申请号：US17869086

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/12 ,  G11C11/22 ,  H01L21/84 ,  H10B51/20 ,  H10B51/30 ,  H10D30/01 ,  H10D30/69 ,  H10D64/01 ,  H10D64/68 ,  H10D86/00 ,  H10D86/01 ,  H10D87/00

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

公开(公告)号：US20240105515A1

公开(公告)日：2024-03-28

申请号：US18521045

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46 ,  H10K71/12 ,  H10K85/20

CPC classification number: H01L21/823412 ,  H01L21/02568 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H10K10/464 ,  H10K10/474 ,  H10K10/484 ,  H10K10/486 ,  H10K71/12 ,  H10K85/221

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US11935890B2

公开(公告)日：2024-03-19

申请号：US17718182

申请日：2022-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Ling-Yen Yeh ,  Carlos H. Diaz ,  Tung-Ying Lee

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H04L9/40 ,  H04L67/303 ,  H04L67/306

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L21/76897 ,  H01L23/53295 ,  H01L23/5384 ,  H01L27/1248 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/7851 ,  H01L29/786 ,  H01L29/78681 ,  H01L29/78684 ,  H04L63/0853 ,  H04L67/303 ,  H04L67/306 ,  H01L29/41791 ,  H01L2029/7858

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

公开(公告)号：US11910617B2

公开(公告)日：2024-02-20

申请号：US17098919

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H10B51/30 ,  H01L29/66 ,  H01L29/786 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H10B51/20

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

公开(公告)号：US11903221B2

公开(公告)日：2024-02-13

申请号：US17156320

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Chun-Chieh Lu ,  Chi On Chui ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H10B63/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H10B61/22 ,  H10B63/34

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.