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    Memory Array Staircase Structure
    34.
    发明申请
    Memory Array Staircase Structure 有权

    公开(公告)号：US20220036931A1

    公开(公告)日：2022-02-03

    申请号：US17081380

    申请日：2020-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: G11C8/14 ,  H01L27/11597 ,  H01L27/105 ,  H01L21/822 ,  H01L21/8239

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

    Reducing Parasitic Capacitance in Semiconductor Devices
    37.
    发明申请
    Reducing Parasitic Capacitance in Semiconductor Devices 有权

    公开(公告)号：US20210376072A1

    公开(公告)日：2021-12-02

    申请号：US17198774

    申请日：2021-03-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Ta Yu ,  Hsiao-Chiu Hsu ,  Feng-Cheng Yang

    IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

    NOVEL 3D RAM SL/BL CONTACT MODULATION
    38.
    发明申请
    NOVEL 3D RAM SL/BL CONTACT MODULATION 有权

    公开(公告)号：US20210375919A1

    公开(公告)日：2021-12-02

    申请号：US17122228

    申请日：2020-12-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/522

    Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

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