公开(公告)号：US20220406629A1

公开(公告)日：2022-12-22

申请号：US17720807

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Chun-Liang Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  G03F7/40

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

公开(公告)号：US20220384606A1

公开(公告)日：2022-12-01

申请号：US17818400

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yi-Hsiu Liu ,  Tsung-Lin Lee ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

公开(公告)号：US20220367632A1

公开(公告)日：2022-11-17

申请号：US17872452

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20220359517A1

公开(公告)日：2022-11-10

申请号：US17371351

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kang Ho ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.

公开(公告)号：US20220359311A1

公开(公告)日：2022-11-10

申请号：US17385561

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US20220301874A1

公开(公告)日：2022-09-22

申请号：US17664930

申请日：2022-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Jie Liu ,  Chun-Feng Nieh ,  Huicheng Chang

IPC: H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L21/266 ,  H01L27/11 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.

公开(公告)号：US11450757B2

公开(公告)日：2022-09-20

申请号：US17013615

申请日：2020-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Wei-Ting Chien ,  Chih-Pin Tsao ,  Hou-Ju Li ,  Tien-Shun Chang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

公开(公告)号：US20220123111A1

公开(公告)日：2022-04-21

申请号：US17075992

申请日：2020-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Che-Fu Chiu ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/10 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/265 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L21/28 ,  H01L21/74

Abstract: A method of forming a semiconductor device includes implanting dopants of a first conductivity type into a semiconductor substrate to form a first well, epitaxially growing a channel layer over the semiconductor substrate, forming a fin from the second semiconductor material, and forming a gate structure over a channel region of the fin. The semiconductor substrate includes a first semiconductor material. Implanting the dopants may be performed at a temperature in a range of 150° C. to 500° C. The channel layer may include a second semiconductor material. The channel layer may be doped with dopants of the first conductivity type.

公开(公告)号：US11245033B2

公开(公告)日：2022-02-08

申请号：US16049358

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. Diaz ,  Chun-Hsiung Lin ,  Huicheng Chang ,  Syun-Ming Jang ,  Chien-Hsun Wang ,  Mao-Lin Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/165 ,  H01L29/51

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

公开(公告)号：US20210335719A1

公开(公告)日：2021-10-28

申请号：US17171320

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3215

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.