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公开(公告)号：US11264359B2
公开(公告)日：2022-03-01
申请号：US17028629
申请日：2020-09-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Kuei Hsu , Ming-Chih Yew , Shu-Shen Yeh , Che-Chia Yang , Po-Yao Lin , Shin-Puu Jeng
IPC: H01L23/495 , H01L23/34 , H01L23/48 , H01L21/00 , H01L21/44 , H01L21/4763 , H01L25/065 , H01L23/538 , H01L21/56 , H01L21/48 , H01L23/31 , H01L23/00
Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.
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公开(公告)号：US20210225785A1
公开(公告)日：2021-07-22
申请号：US17222044
申请日：2021-04-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Po-Yao Chuang , Ming-Chih Yew , Shin-Puu Jeng
Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.
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公开(公告)号：US10665559B2
公开(公告)日：2020-05-26
申请号：US16129736
申请日：2018-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Kuei Hsu , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Lin , Shin-Puu Jeng
IPC: H01L23/00 , H01L23/31 , H01L21/56 , H01L21/768
Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
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34.发明申请公开(公告)号：US20190035772A1
公开(公告)日：2019-01-31
申请号：US15660968
申请日：2017-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Li-Hsien Huang , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hua-Wei Tseng , Ming-Chih Yew , Yi-Jen Lai , Ming-Shih Yeh
Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.
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公开(公告)号：US20150194389A1
公开(公告)日：2015-07-09
申请号：US14151217
申请日：2014-01-09
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Ming-Chih Yew , Fu-Jen Li , Po-Yao Lin , Kuo-Chuan Liu
IPC: H01L23/00 , H01L23/367
CPC classification number: H01L23/562 , H01L23/3128 , H01L23/36 , H01L23/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/0002 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
Abstract translation: 在散热器盖的粘合表面和半导体封装的顶表面之间，除了吊具粘合剂层之外，还提供了几个翘曲控制粘合剂层。 翘曲控制粘合剂层设置在散热器盖的粘合表面的拐角区域，以减少半导体器件封装的高温翘曲。
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Patent Agency Ranking
公开(公告)号：US20240371783A1
公开(公告)日：2024-11-07
申请号：US18778258
申请日：2024-07-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Kuei Hsu , Ming-Chih Yew , Shu-Shen Yeh , Che-Chia Yang , Po-Yao Lin , Shin-Puu Jeng
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L25/065 , H01L25/07
Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.
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公开(公告)号：US20240363511A1
公开(公告)日：2024-10-31
申请号：US18770022
申请日：2024-07-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Kuei Hsu , Ming-Chih Yew , Po-Yao Lin , Shuo-Mao Chen , Feng-Cheng Hsu , Shin-Puu Jeng
IPC: H01L23/498 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/18
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/563 , H01L23/49838 , H01L24/81 , H01L25/0655 , H01L25/18 , H01L2224/81815
Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.
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公开(公告)号：US12100664B2
公开(公告)日：2024-09-24
申请号：US18352595
申请日：2023-07-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Kuei Hsu , Ming-Chih Yew , Shu-Shen Yeh , Che-Chia Yang , Po-Yao Lin , Shin-Puu Jeng
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L25/065 , H01L25/07
CPC classification number: H01L23/5386 , H01L21/4857 , H01L21/561 , H01L23/3185 , H01L23/481 , H01L23/49838 , H01L23/5383 , H01L24/06 , H01L24/09 , H01L24/20 , H01L24/30 , H01L24/82 , H01L25/0652 , H01L25/0655 , H01L25/072 , H01L21/486 , H01L23/3128
Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.
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公开(公告)号：US20240304572A1
公开(公告)日：2024-09-12
申请号：US18664508
申请日：2024-05-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Po-Yao Chuang , Ming-Chih Yew , Shin-Puu Jeng
IPC: H01L23/66 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L23/538 , H01Q1/22 , H01Q9/04 , H01Q9/28 , H01Q21/06
CPC classification number: H01L23/66 , H01L21/566 , H01L23/3107 , H01L23/481 , H01L23/49822 , H01L23/5383 , H01L24/09 , H01L24/17 , H01Q1/2283 , H01Q9/045 , H01Q9/285 , H01Q21/062 , H01Q21/065 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2223/6677 , H01L2224/02372 , H01L2224/02379 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.
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公开(公告)号：US12021045B2
公开(公告)日：2024-06-25
申请号：US18186348
申请日：2023-03-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Hao Tsai , Po-Yao Chuang , Ming-Chih Yew , Shin-Puu Jeng
IPC: H01L23/66 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L23/538 , H01Q1/22 , H01Q9/04 , H01Q9/28 , H01Q21/06
CPC classification number: H01L23/66 , H01L21/566 , H01L23/3107 , H01L23/481 , H01L23/49822 , H01L23/5383 , H01L24/09 , H01L24/17 , H01Q1/2283 , H01Q9/045 , H01Q9/285 , H01Q21/062 , H01Q21/065 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2223/6677 , H01L2224/02372 , H01L2224/02379 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.
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