公开(公告)号：US11222915B2

公开(公告)日：2022-01-11

申请号：US16040567

申请日：2018-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L21/00 ,  H01L27/146 ,  H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.

公开(公告)号：US20210028219A1

公开(公告)日：2021-01-28

申请号：US17070430

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

公开(公告)号：US10014340B2

公开(公告)日：2018-07-03

申请号：US14980386

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien Yang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Shyh-Fann Ting ,  Chun-Yuan Chen

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/107

CPC classification number: H01L27/14634 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/03529 ,  H01L31/107

Abstract: The present disclosure relates to a stacked SPAD image sensor with a CMOS Chip and an imaging chip bonded together, to improve the fill factor of the SPAD image sensor, and an associated method of formation. In some embodiments, the imaging chip has a plurality of SPAD cells disposed within a second substrate. The CMOS Chip has a first interconnect structure disposed over a first substrate. The imaging chip has a second interconnect structure disposed between the second substrate and the first interconnect structure. The CMOS Chip and the imaging chip are bonded together through along an interface disposed between the first interconnect structure and the second interconnect structure.

公开(公告)号：US20170243903A1

公开(公告)日：2017-08-24

申请号：US15590264

申请日：2017-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Fann Ting ,  Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: The present disclosure relates to a semiconductor image sensor device. In some embodiments, the semiconductor image sensor device includes a semiconductor substrate having a first surface configured to receive incident radiation. A plurality of sensor elements are arranged within the semiconductor substrate. A first charged layer is arranged on an entirety of a second surface of the semiconductor substrate facing an opposite direction as the first surface. The second surface is between the first charged layer and the first surface of the semiconductor substrate.

公开(公告)号：US20170186798A1

公开(公告)日：2017-06-29

申请号：US14980386

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien Yang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Shyh-Fann Ting ,  Chun-Yuan Chen

IPC: H01L27/146 ,  H01L31/107

CPC classification number: H01L27/14634 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/03529 ,  H01L31/107

Abstract: The present disclosure relates to a stacked SPAD image sensor with a CMOS Chip and an imaging chip bonded together, to improve the fill factor of the SPAD image sensor, and an associated method of formation. In some embodiments, the imaging chip has a plurality of SPAD cells disposed within a second substrate. The CMOS Chip has a first interconnect structure disposed over a first substrate. The imaging chip has a second interconnect structure disposed between the second substrate and the first interconnect structure. The CMOS Chip and the imaging chip are bonded together through along an interface disposed between the first interconnect structure and the second interconnect structure.

公开(公告)号：US20170133414A1

公开(公告)日：2017-05-11

申请号：US14935819

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

公开(公告)号：US20170117309A1

公开(公告)日：2017-04-27

申请号：US14923635

申请日：2015-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

公开(公告)号：US09437645B1

公开(公告)日：2016-09-06

申请号：US14663918

申请日：2015-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Yu Chou ,  Chun-Hao Chuang ,  Chien-Hsien Tseng ,  Shyh-Fann Ting ,  Wei-Chieh Chiang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A semiconductor structure for back side illumination (BSI) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate. A composite grid includes a metal grid and a low refractive index (low-n) grid. The metal grid includes first openings overlying the semiconductor substrate and corresponding to ones of the photodiodes. The low-n grid includes second openings overlying the semiconductor substrate and corresponding to ones of the photodiodes. Color filters are arranged in the first and second openings of the corresponding photodiodes and have a refractive index greater than a refractive index of the low-n grid. Upper surfaces of the color filters are offset relative to an upper surface of the composite grid. A method for manufacturing the BSI pixel sensors is also provided.

Abstract translation: 提供了用于背面照明（BSI）像素传感器的半导体结构。 光电二极管布置在半导体衬底内。 复合网格包括金属网格和低折射率（low-n）网格。 金属栅格包括覆盖半导体衬底并对应于一个光电二极管的第一开口。 低n栅格包括覆盖半导体衬底并对应于光电二极管中的一个的第二开口。 彩色滤光器布置在相应的光电二极管的第一和第二开口中并且具有大于低n栅格的折射率的折射率。 滤色片的上表面相对于复合网格的上表面偏移。 还提供了用于制造BSI像素传感器的方法。

公开(公告)号：US12278250B2

公开(公告)日：2025-04-15

申请号：US17321909

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Feng-Chi Hung ,  Shyh-Fann Ting

IPC: H01L27/146

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

公开(公告)号：US11545513B2

公开(公告)日：2023-01-03

申请号：US17187955

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146 ,  H04N5/365 ,  H01L21/762 ,  H01L31/0216

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.