公开(公告)号：US20220122972A1

公开(公告)日：2022-04-21

申请号：US17567476

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20210359109A1

公开(公告)日：2021-11-18

申请号：US17101291

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US20210242206A1

公开(公告)日：2021-08-05

申请号：US16837563

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion-is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20210125859A1

公开(公告)日：2021-04-29

申请号：US16870389

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/3065

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US20210125833A1

公开(公告)日：2021-04-29

申请号：US16811079

申请日：2020-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

公开(公告)号：US12166096B2

公开(公告)日：2024-12-10

申请号：US18301554

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US11942363B2

公开(公告)日：2024-03-26

申请号：US17818608

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/30608 ,  H01L21/30655 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US11764222B2

公开(公告)日：2023-09-19

申请号：US17567476

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L21/311 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/66545

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20230253470A1

公开(公告)日：2023-08-10

申请号：US18301554

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L21/82385 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78642

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20230214575A1

公开(公告)日：2023-07-06

申请号：US18183056

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Szu-ju Huang ,  Shih-Yao Lin ,  Shih Feng Hong ,  Yin-An Chen

IPC: G06F30/398 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/327 ,  G06F30/396 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/396 ,  G06F30/3315 ,  G06F2119/12

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.