公开(公告)号：US5652730A

公开(公告)日：1997-07-29

申请号：US648607

申请日：1996-05-15

申请人： Takashi Kono ,  Kiyohiro Furutani ,  Mikio Asakura ,  Hideto Hidaka

发明人： Takashi Kono ,  Kiyohiro Furutani ,  Mikio Asakura ,  Hideto Hidaka

IPC分类号： G11C11/407 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C8/12

摘要： A DRAM includes an internal boosting circuit, a global power-line, a plurality of blocks, a row decoder, and a POR generating circuit. Each block includes word lines, local power-lines, AND gates, drive transistors, and word line drivers. The AND gate turns a corresponding drive transistor on/off in response to a power on reset signal /POR and a corresponding block select signal. Therefore, all the local boosted power-lines are connected to the global boosted power-line during a power on reset period, whereby all the local boosted power-lines are initially charged up to boosted power supply potential Vpp.

摘要翻译： DRAM包括内部升压电路，全局电源线，多个块，行解码器和POR发生电路。 每个块包括字线，本地电源线，与门，驱动晶体管和字线驱动器。 AND门响应于上电复位信号/ POR和相应的块选择信号而使相应的驱动晶体管导通/截止。 因此，所有本地升压电源线​​在上电复位期间连接到全局升压电源线​​，由此所有本地升压电源线​​最初都被充电至提升电源电位Vpp。

公开(公告)号：US5588130A

公开(公告)日：1996-12-24

申请号：US283367

申请日：1994-08-01

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC分类号： G06F12/08 ,  G11C7/10 ,  G06F13/00 ,  G11C15/00

CPC分类号： G06F12/0893 ,  G11C7/1021

摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

公开(公告)号：US5426615A

公开(公告)日：1995-06-20

申请号：US224461

申请日：1994-04-07

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C5/02

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines include lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of a power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。 电源和接地线包括与感测放大器带平行并接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。 每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 布置成网状的多个电源和接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。

公开(公告)号：US5321646A

公开(公告)日：1994-06-14

申请号：US865142

申请日：1992-04-08

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi

IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4074 ,  G11C5/02 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C7/065

摘要： A power supply line is disposed parallel to a sense amplifier train including a plurality of sense amplifiers at the side of each subarray. The power supply line is connected to the sense amplifier included in the sense amplifier train via a plurality of drive transistors and a sense amplifier drive line.

摘要翻译： 电源线平行于包括在每个子阵列一侧的多个读出放大器的读出放大器串列布置。 电源线通过多个驱动晶体管和读出放大器驱动线路连接到包括在读出放大器列中的读出放大器。

公开(公告)号：US5014241A

公开(公告)日：1991-05-07

申请号：US337219

申请日：1989-04-12

申请人： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C5/025 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  G11C5/063 ,  G11C7/14 ,  G11C7/18

摘要： Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

摘要翻译： 读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。 存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。 在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。 存储在存储单元中的信息被读出到两个位线之间的另一位线上。

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US06404691B1

公开(公告)日：2002-06-11

申请号：US08472770

申请日：1995-06-07

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC分类号： G11C700

CPC分类号： G06F12/0893 ,  G11C7/1021

摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

公开(公告)号：US06301169B1

公开(公告)日：2001-10-09

申请号：US09658011

申请日：2000-09-08

申请人： Shigeru Kikuda ,  Takeshi Hamamoto ,  Mikio Asakura

发明人： Shigeru Kikuda ,  Takeshi Hamamoto ,  Mikio Asakura

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C29/40

摘要： In a set of memory cells selected by one column select line, a memory cell of at least 1 bit is connected to an internal data line that is different from the internal data line to which another memory cell in the same set is connected. An internal data line pair is connected to a data terminal. Thus, data having different logic levels can be written into adjacent memory cells even in an IO compression test mode.

摘要翻译： 在由一列选择线选择的一组存储器单元中，至少1位的存储单元连接到内部数据线，该内部数据线与同一组中的另一个存储单元连接到的内部数据线不同。 内部数据线对连接到数据终端。 因此，即使在IO压缩测试模式下，也可以将具有不同逻辑电平的数据写入相邻存储单元。

公开(公告)号：US06301163B1

公开(公告)日：2001-10-09

申请号：US09385582

申请日：1999-08-27

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C2900

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

摘要翻译： 一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器 正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。 控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。 所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

公开(公告)号：US06249462B1

公开(公告)日：2001-06-19

申请号：US09557867

申请日：2000-04-24

申请人： Koji Tanaka ,  Jun Nakai ,  Yasuhiko Tsukikawa ,  Mikio Asakura

发明人： Koji Tanaka ,  Jun Nakai ,  Yasuhiko Tsukikawa ,  Mikio Asakura

IPC分类号： G11C1604

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C11/4093

摘要： An output buffer includes a pull up transistor of N type field effect to charge a data output terminal by an external power supply potential Vdd in a high level data output operation, and a pull down transistor of N type field effect to discharge the data output terminal to a ground potential Vss in a low level data output operation. The substrate potential of the pull up NMOS transistor is set to a potential of a level higher than the normal case in a high level data output operation. As a result, the output buffer can speedily charge the data terminal in a high level data output operation.

摘要翻译： 输出缓冲器包括N型场效应的上拉晶体管，用于在高电平数据输出操作中由外部电源电位Vdd对数据输出端子充电;以及N型场效应的下拉晶体管，以对数据输出端子 到低电平数据输出操作中的地电位Vss。 在高电平数据输出操作中，上拉NMOS晶体管的衬底电位被设置为高于正常情况的电平。 结果，输出缓冲器可以在高电平数据输出操作中对数据终端进行快速充电。