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136 条记录 (耗时 0.043 秒)

    DUAL-PERSONALITY EXTENDED USB PLUGS AND RECEPTACLES USING WITH PCBA AND CABLE ASSEMBLY
    32.
    发明申请
    DUAL-PERSONALITY EXTENDED USB PLUGS AND RECEPTACLES USING WITH PCBA AND CABLE ASSEMBLY 有权
    使用PCBA和电缆组件的双重个性扩展USB插头和插座

    公开(公告)号：US20120309231A1

    公开(公告)日：2012-12-06

    申请号：US13585704

    申请日：2012-08-14

    申请人： David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： H01R13/66

    CPC分类号： H01R13/6658

    摘要： A USB plug receptacle includes a connector substrate having a tongue portion having a first set of electrical contact pins disposed on a top surface of the tongue portion, a second set of a plurality of electrical pins disposed on a bottom surface of the tongue portion, a third set of electrical contact pins disposed on an opposite end of the tongue portion. The USB plug receptacle further includes a metal case made of a sheet of electrically conductive metal plate by blanking the sheet into a generally tubular shape to receive and enclose the connector substrate. When the connector substrate is inserted into the metal case, the third set of electrical contact pins are exposed outside of the metal case and the third set of electrical contact pins can be mounted on first and second sets of electrical contact pads of a printed circuit board assembly.

    摘要翻译： USB插头插座包括具有舌部的连接器基底，舌部具有设置在舌部的顶表面上的第一组电接触针，设置在舌部的底表面上的多个电针的第二组， 设置在舌部相对端的第三组电接触针。 USB插头插座还包括由导电金属板片制成的金属外壳，通过将片材冲压成大致管状形状以接收和封闭连接器基板。 当连接器基板插入金属壳体中时，第三组电接触销被暴露在金属外壳的外部，并且第三组电接触销可以安装在印刷电路板的第一和第二组电接触焊盘上 部件。

    Multi-level cell (MLC) dual personality extended fiber optic flash memory device
    33.
    发明授权
    Multi-level cell (MLC) dual personality extended fiber optic flash memory device 失效
    多级单元（MLC）双重人格扩展光纤闪存设备

    公开(公告)号：US08061905B2

    公开(公告)日：2011-11-22

    申请号：US12111872

    申请日：2008-04-29

    申请人： Abraham Ma ,  I-Kang Yu ,  David Nguyen ,  Charles C. Lee ,  Ming-Shiang Shen

    发明人： Abraham Ma ,  I-Kang Yu ,  David Nguyen ,  Charles C. Lee ,  Ming-Shiang Shen

    IPC分类号： G02B6/38

    CPC分类号： G06K19/07732

    摘要： A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data.

    摘要翻译： 多级单元（MLC）双人格扩展光纤闪存驱动器包括连接到双人格扩展光纤闪存驱动器的MLC双人格扩展光纤通用串行总线（USB）插头连接器，并且可移除地连接到 主办。 该连接器适用于接收电气数据和光学数据。 位于闪存驱动器上的收发器用于将接收的电数据转换为光学数据或将接收到的光学数据转换为电气数据。

    Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device
    34.
    发明授权
    Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device 失效
    在基于大容量多级单元（MLC）的闪存设备中管理存储器地址的方法和系统

    公开(公告)号：US07886108B2

    公开(公告)日：2011-02-08

    申请号：US12025706

    申请日：2008-02-04

    申请人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    发明人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    IPC分类号： G06F13/16

    CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G11C11/5621 ,  G11C16/0408 ,  G11C16/349 ,  G11C16/3495

    摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

    摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

    Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices
    35.
    发明授权
    Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices 有权
    存储器模块具有配置用于在同步存储器件上顺序到达信号的信号线

    公开(公告)号：US07870322B2

    公开(公告)日：2011-01-11

    申请号：US12426083

    申请日：2009-04-17

    申请人： Haw-Jyh Liaw ,  David Nguyen

    发明人： Haw-Jyh Liaw ,  David Nguyen

    IPC分类号： G06F13/42

    CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    摘要： A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

    摘要翻译： 存储器模块包括用于承载第一信号的第一信号线。 第一信号线具有（i）沿着存储器模块的长度设置并耦合到终端的第一线段，以及（ii）沿着存储器模块的宽度设置并耦合到边缘指状物的第二线段。 第一线段和第二线段在转弯处耦合在一起。 第一同步存储器件和第二同步存储器件耦合到第一线段。 第一信号以顺序的方式到达第一同步存储器件和第二同步存储器件。 存储器模块包括沿着第一信号线路线路由的时钟线。 时钟信号沿着沿着第一信号线的第一信号沿着顺序到达第一同步存储器件和第二同步存储器件。

    Slide flash memory devices
    36.
    发明授权
    Slide flash memory devices 有权
    滑动闪存设备

    公开(公告)号：US07806705B2

    公开(公告)日：2010-10-05

    申请号：US12604309

    申请日：2009-10-22

    申请人： Frank I-Kang Yu ,  David Nguyen ,  Jim Chin-Nan Ni ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： Frank I-Kang Yu ,  David Nguyen ,  Jim Chin-Nan Ni ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： H01R13/44

    CPC分类号： C09D17/001

    摘要： A portable USB device with an improved configuration is described herein. According to one embodiment, a portable USB device includes a core unit having a USB plug connector coupled to one or more flash memory devices and a flash controller disposed therein, where the flash controller is capable of exchanging data with a host via the USB plug connector using a bulk-only-transfer protocol. The portable USB device further includes a housing for enclosing the core unit, including a front end opening to allow the USB plug connector to be deployed. The portable USB device further includes a core unit carrier for carrying the core unit for deploying and retracting the core unit, including a slide button to allow a finger of a user to slide the USB plug connector of the core unit in and out of the housing via the front end opening of the housing.

    摘要翻译： 本文描述了具有改进的配置的便携式USB设备。 根据一个实施例，便携式USB设备包括具有耦合到一个或多个闪存设备的USB插头连接器和设置在其中的闪存控制器的核心单元，其中闪存控制器能够经由USB插头连接器与主机交换数据 使用批量传输协议。 便携式USB设备还包括用于封装核心单元的壳体，包括前端开口以允许USB插头连接器被部署。 便携式USB装置还包括用于承载用于部署和缩回核心单元的核心单元的核心单元载体，包括滑动按钮，以允许用户的手指将核心单元的USB插头连接器滑入和移出壳体 通过外壳的前端开口。

    SYSTEM AND METHOD FOR AUTOMATED RECONCILIATION OF PURCHASE ORDERS
    38.
    发明申请
    SYSTEM AND METHOD FOR AUTOMATED RECONCILIATION OF PURCHASE ORDERS 审中-公开
    用于自动重新购买订单的系统和方法

    公开(公告)号：US20100153241A1

    公开(公告)日：2010-06-17

    申请号：US12333965

    申请日：2008-12-12

    申请人： Randy Rucker ,  Lisa Rivers ,  Brian Lochhead ,  David Nguyen

    发明人： Randy Rucker ,  Lisa Rivers ,  Brian Lochhead ,  David Nguyen

    IPC分类号： G06Q10/00

    CPC分类号： G06Q10/087 ,  G06Q40/12

    摘要： A system and method for reconciling transaction data, including identifying one or more transactions to be reconciled; aggregating one or more potential matching purchase orders; and creating a proposal that identifies one or more purchase orders that may correlate to the transaction to be reconciled, wherein creating a proposal comprises performing one or more search iterations to identify one or more purchase orders that fit within one or more parameters of the search iterations.

    摘要翻译： 一种用于协调交易数据的系统和方法，包括识别要协调的一个或多个交易; 汇总一个或多个潜在的匹配采购订单; 以及创建标识一个或多个可以与要协调的交易相关联的采购订单的提案，其中创建提案包括执行一个或多个搜索迭代以识别适合于搜索迭代的一个或多个参数内的一个或多个采购订单 。

    Memory module having a clock line and termination
    39.
    发明授权
    Memory module having a clock line and termination 有权
    内存模块具有时钟线和终端

    公开(公告)号：US07523247B2

    公开(公告)日：2009-04-21

    申请号：US11683916

    申请日：2007-03-08

    申请人： Haw-Jyh Liaw ,  David Nguyen

    发明人： Haw-Jyh Liaw ,  David Nguyen

    IPC分类号： G06F13/42

    CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    摘要： A memory module includes a signal line to carry a signal that traverses the signal line until reaching a termination at an end of the signal line. The module includes a clock line to carry a clock signal that traverses the clock line alongside the signal until the signal reaches a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

    摘要翻译： 存储器模块包括用于承载穿过信号线的信号的信号线，直到在信号线的末端达到终止。 该模块包括一个时钟线，用于携带沿信号旁边穿过时钟线的时钟信号，直到信号在时钟线的末端达到第二个终止。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件并且在信号和时钟信号到达第一存储器件之后。