公开(公告)号：US08004289B2

公开(公告)日：2011-08-23

申请号：US12198221

申请日：2008-08-26

申请人： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

发明人： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC分类号： G01R27/26 ,  G01R31/308

CPC分类号： H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

摘要翻译： 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US07960245B2

公开(公告)日：2011-06-14

申请号：US12029575

申请日：2008-02-12

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

IPC分类号： H01L21/30

CPC分类号： H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

公开(公告)号：US07732294B2

公开(公告)日：2010-06-08

申请号：US12170464

申请日：2008-07-10

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

摘要翻译： 一种半导体器件的方法。 提供基板。 衬底内至少有一个金属布线层。 绝缘层沉积在衬底的表面上。 使用图案化板工艺在绝缘层内形成电感器。 在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

公开(公告)号：US20090273084A1

公开(公告)日：2009-11-05

申请号：US12115056

申请日：2008-05-05

申请人： Stephen Peter Ayotte ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Kimball M. Watson

发明人： Stephen Peter Ayotte ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Kimball M. Watson

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/522 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/57 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

摘要翻译： 一种结构和方法。 该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测 通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

公开(公告)号：US20090179284A1

公开(公告)日：2009-07-16

申请号：US12013514

申请日：2008-01-14

申请人： Jeffrey Peter Gambino

发明人： Jeffrey Peter Gambino

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90

摘要： A semiconductor structure and a method for forming the same. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.

摘要翻译： 半导体结构及其形成方法。 该结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）栅极电介质区，和（iv）栅电极区，（v） 栅电极区上的多个互连层，以及（vi）第一和第二空间。 栅极电介质区域设置在沟道区域和栅电极区域之间并与其直接物理接触。 栅电极区域设置在栅极电介质区域和互连层之间并与其直接物理接触。 第一和第二空间与栅电极区域直接物理接触。 第一空间设置在第一源极/漏极区域和栅极电极区域之间。 第二空间设置在第二源极/漏极区域和栅极电极区域之间。

公开(公告)号：US20080308948A1

公开(公告)日：2008-12-18

申请号：US12198221

申请日：2008-08-26

申请人： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

发明人： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC分类号： H01L23/52 ,  H01L21/66

CPC分类号： H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

摘要翻译： 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US20080261121A1

公开(公告)日：2008-10-23

申请号：US11738004

申请日：2007-04-20

申请人： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

发明人： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/30 ,  G03F1/48 ,  G03F1/54

摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.

摘要翻译： 光掩模和制造光掩模的方法。 所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。 保形层通过氧化形成。

公开(公告)号：US20080261120A1

公开(公告)日：2008-10-23

申请号：US11737956

申请日：2007-04-20

申请人： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

发明人： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/30 ,  G03F1/48 ,  G03F1/54

摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.

摘要翻译： 光掩模和制造光掩模的方法。 所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。 保形层通过氧化形成。

公开(公告)号：US07193423B1

公开(公告)日：2007-03-20

申请号：US11275112

申请日：2005-12-12

申请人： Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

发明人： Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC分类号： G01R27/26 ,  G01R31/02

CPC分类号： H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

摘要翻译： 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。 第一个方向基本上平行于共同的表面。

公开(公告)号：US06326260B1

公开(公告)日：2001-12-04

申请号：US09599703

申请日：2000-06-22

申请人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

发明人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823462 ,  H01L27/10873

摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.

摘要翻译： 提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。 具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层 形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层 所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及 所述多晶硅层在所述导体材料层上形成氮化物覆盖层 形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。