公开(公告)号：US08110924B2

公开(公告)日：2012-02-07

申请号：US12408390

申请日：2009-03-20

申请人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Daisuke Minohara

发明人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Daisuke Minohara

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/585 ,  H01L23/522 ,  H01L23/552 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.

摘要翻译： 在DC-DC转换器中，在硅衬底上设置多层布线层，并且在硅衬底和多层布线层中形成控制输入电路和输出电路的控制电路。 此外，设置覆盖多层布线层的密封树脂层和连接到多层布线层的最上布线的连接构件，其穿透密封树脂层并具有从密封树脂层的上表面突出的上端部。 连接构件的上端部由突出电极形成。 与输出电路的端子连接的连接构件的水平横截面面积大于与控制电路的端子连接的连接构件的水平截面积。

公开(公告)号：US08067801B2

公开(公告)日：2011-11-29

申请号：US12181692

申请日：2008-07-29

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L29/735

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

摘要翻译： 提供了一种半导体器件，其包括形成在半导体层中的第一晶体管和第二晶体管。 第一晶体管包括第一源极区域和与第一源极区域夹持第一栅电极的第一漏极区域。 第二晶体管包括LDD区和漂移区，其夹持具有LDD区的第二栅极，以及与漂移区相邻的第二漏极区，以将第二栅电极夹在第二源极区。 第一栅电极具有形成在其侧面上的第一侧壁，并且第二栅电极具有形成在其侧面上的第二侧壁。 沿着第一绝缘体的前者的宽度与第二绝缘体的宽度不同。

公开(公告)号：US20110095369A1

公开(公告)日：2011-04-28

申请号：US12878979

申请日：2010-09-09

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

IPC分类号： H01L29/772

CPC分类号： H01L29/0692 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.

摘要翻译： 根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。 源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。 第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。 第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

公开(公告)号：US07906808B2

公开(公告)日：2011-03-15

申请号：US12476147

申请日：2009-06-01

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

公开(公告)号：US20100176449A1

公开(公告)日：2010-07-15

申请号：US12688459

申请日：2010-01-15

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/266 ,  H01L21/823425 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device, includes: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type, the second semiconductor region having a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the first semiconductor region; a source region of a second conductivity type provided on the first semiconductor region; a drain region of the second conductivity type provided on the second semiconductor region; an insulating film provided on the semiconductor layer between the source region and the drain region; a gate electrode provided on the insulating film; and a drift region of the second conductivity type provided in a surface side portion of the semiconductor layer between the gate electrode and the drain region, the drift region being in contact with the drain region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the drain region.

摘要翻译： 一种半导体器件，包括：半导体层，包括第一导电类型的第一半导体区域和第一导电类型的第二半导体区域，所述第二半导体区域具有低于第一导电类型杂质浓度的第一导电类型杂质浓度 第一个半导体区域; 设置在第一半导体区域上的第二导电类型的源极区域; 设置在所述第二半导体区域上的所述第二导电类型的漏极区域; 设置在源极区域和漏极区域之间的半导体层上的绝缘膜; 设置在绝缘膜上的栅电极; 以及设置在所述半导体层的栅极电极和漏极区域的表面侧部分中的所述第二导电类型的漂移区域，所述漂移区域与所述漏极区域接触并且具有低于第二导电型杂质浓度的第二导电类型杂质浓度 漏极区的导电型杂质浓度。

公开(公告)号：US20090032869A1

公开(公告)日：2009-02-05

申请号：US12181692

申请日：2008-07-29

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

摘要翻译： 提供了一种半导体器件，其包括形成在半导体层中的第一晶体管和第二晶体管。 第一晶体管包括第一源极区域和与第一源极区域夹持第一栅电极的第一漏极区域。 第二晶体管包括LDD区和漂移区，其夹持具有LDD区的第二栅极，以及与漂移区相邻的第二漏极区，以将第二栅电极夹在第二源极区。 第一栅电极具有形成在其侧面上的第一侧壁，并且第二栅电极具有形成在其侧面上的第二侧壁。 沿着第一绝缘体的前者的宽度与第二绝缘体的宽度不同。

公开(公告)号：US20060097292A1

公开(公告)日：2006-05-11

申请号：US11261531

申请日：2005-10-31

申请人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Norio Yasuhara

发明人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： A semiconductor device includes a second conductivity type layer selectively formed by changing impurity concentrations on a semiconductor substrate, a first conductivity type source region formed on the second conductivity type layer, a first conductivity type drain region formed on the second conductivity type layer apart from the first conductivity type source region, a gate electrode formed between the first conductivity type source region and the first conductivity type drain region across an insulation film, and a second conductivity type contact layer formed adjacent to the first conductivity type source region, wherein the second conductivity type layer in the source region side has a higher impurity concentration than the impurity concentration of the second conductivity type layer in the drain region side.

摘要翻译： 半导体器件包括通过改变半导体衬底上的杂质浓度选择性地形成的第二导电类型层，形成在第二导电类型层上的第一导电型源极区，形成在第二导电类型层上的第一导电类型漏极区， 第一导电型源极区，形成在绝缘膜之间的第一导电型源极区域和第一导电型漏极区域之间的栅电极和与第一导电型源极区域相邻形成的第二导电型接触层，其中第二导电型源极区域 源极区侧的杂质浓度比漏区侧的第二导电型层的杂质浓度高。

公开(公告)号：US6064086A

公开(公告)日：2000-05-16

申请号：US72460

申请日：1998-05-05

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki ,  Norio Yasuhara

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki ,  Norio Yasuhara

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： An n-type buffer layer and a p-type base layer are formed in the surface of the n.sup.- -type drift layer. A p.sup.+ -type drain layer is formed in the surface of the n-type buffer layer. An n.sup.+ -type source layer and a p.sup.+ -type contact layer are formed in the surface of the p-type base layer. A main gate electrode is arranged to face, through a gate oxide film, a surface of the p-type base layer which is interposed between the n.sup.+ -type source layer and the n.sup.- -type drift layer. An n-type relay layer is formed in the surface of the n.sup.- -type drift layer to face the n.sup.+ -type source layer through the p-type base layer under the main gate electrode. The n-type relay layer extends from the n.sup.- -type drift layer into the p-type base layer. The n-type relay layer decreases the channel resistance.

摘要翻译： 在n型漂移层的表面形成n型缓冲层和p型基底层。 在n型缓冲层的表面形成p +型漏极层。 在p型基底层的表面形成n +型源极层和p +型接触层。 主栅极布置成通过栅极氧化膜面对介于n +型源极层和n型漂移层之间的p型基极层的表面。 在n型漂移层的表面形成n型继电器层，通过主栅电极下方的p型基极层面对n +型源极层。 n型继电器层从n型漂移层延伸到p型基极层。 n型继电器层降低了通道电阻。

公开(公告)号：US5640040A

公开(公告)日：1997-06-17

申请号：US481097

申请日：1995-06-07

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura ,  Hideyuki Funaki

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286 ,  H01L29/78603 ,  H01L2924/0002

摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.

摘要翻译： 一种高耐压电压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区 形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。 第一杂质区由扩散层形成。 扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

公开(公告)号：US5592014A

公开(公告)日：1997-01-07

申请号：US484864

申请日：1995-06-07

申请人： Hideyuki Funaki ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura

发明人： Hideyuki Funaki ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yoshihiro Yamaguchi ,  Ichiro Omura

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L21/76264 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286 ,  H01L2924/0002

摘要： A high breakdown voltage semiconductor apparatus comprises a substrate having an insulating layer formed thereon, a high resistance semiconductor layer of a first conductivity type formed on said insulating layer, a base region of the first conductivity type formed selectively in a surface region of the high resistance semiconductor layer, a drift region of a second conductivity type formed selectively in the surface region of the high resistance semiconductor layer so as not to reach the insulating layer, a source region of the second conductivity type formed in the base region, a drain region formed in the drift region, a gate electrode formed on a region between the source region and the drift region, with a gate insulating film interposed between the gate electrode and the region between the source region and the drift region, a source electrode provided in contact with the base region and the source region, a drain electrode provided in contact with the drain region. The dosage of impurities in the high resistance semiconductor layer is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage of impurities in the drift layer is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2.

摘要翻译： 一种高耐压电压半导体装置，包括：在其上形成有绝缘层的基板，形成在所述绝缘层上的第一导电类型的高电阻半导体层，所述第一导电类型的基极区选择性地形成在所述高电阻的表面区域中 半导体层，选择性地形成在高电阻半导体层的表面区域中以便不到达绝缘层的第二导电类型的漂移区域，形成在基极区域中的第二导电类型的源极区域，形成的漏极区域 在漂移区域中，形成在源极区域和漂移区域之间的区域上的栅电极，栅极绝缘膜插入在栅极电极和源极区域与漂移区域之间的区域中，源极电极与 所述基极区域和所述源极区域，设置成与所述漏极区域接触的漏极电极。 高电阻半导体层中的杂质用量为2×10 12 cm -2至3×10 12 cm -2，漂移层中的杂质用量为1×10 12 cm -2至2×10 12 cm -2。